Detecting modification to computer memory by a DMA device

• US 6,549,959 B1
• Filed: 11/04/1999
• Issued: 04/15/2003
• Est. Priority Date: 08/30/1999
• Status: Expired due to Term

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Van Dyke, Korbin S., Yates, John S., Reese, David L.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Mai, Rijue
• Application Number:
  US09/434,198
• Time in Patent Office: 1,258 Days
• Field of Search: 710/22, 710/1, 710/23, 710/28, 710/65, 710/107, 710/125, 710/24, 710/25, 710/26, 710/33, 711/144, 711/146, 711/170, 711/203, 711/117, 711/118, 711/145, 711/206
• US Class Current: 710/22
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45554 Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory. DMA (direct memory access) monitoring circuitry and/or software is designed to monitor DMA memory write transactions to a main memory of a computer by a DMA device of the computer; to detect when the first representation is overwritten by a DMA memory write transaction initiated by the second process, without the second process informing the first process of the DMA memory write transaction, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction; to record an indication of a location in the main memory written by the DMA memory write transaction, the DMA monitoring circuitry designed to operate without being informed of the DMA memory write transaction by a CPU of the computer before initiation of the DMA memory write transaction, and to provide the indication to the CPU on request; and to report to the first process that the first representation is overwritten by a DMA memory write transaction. The DMA monitoring circuitry includes a plurality of registers outside the address space of the main memory, each register including an address tag and a vector of memory cells, and control circuitry designed to establish an association between a one of the plurality of registers with a region of the memory when a modification to the region is detected by setting the address tag of the one register to an approximation of the address of the region, and to set the values of the memory cells of the vector to record a fine indication of the address of a memory location modified, the control circuitry being operable without continuing supervisory control of a CPU of the computer. Circuitry is designed to record indications of modification to pages of the main memory into the registers. Read circuitry is designed to respond to a read request from the CPU by providing an address of a modified memory location. The virtual memory management tables do not provide backing store for the modification indications stored in the registers.

Claims

1. Computer circuitry, comprising:

a CPU programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation;

a main memory divided into pages for management by a virtual memory manager, the manager programmed to manage the pages using a table stored in the memory;

DMA (direct memory access) monitoring circuitry and software designed;

to monitor DMA memory write transactions to a main memory of a computer by a DMA device of the computer;

to detect when the first representation is overwritten by a DMA memory write transaction initiated by the second process, without the second process informing the first process of the DMA memory write transaction, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction;

to record an indication of a location in the main memory written by the DMA memory write transaction, the DMA monitoring circuitry designed to operate without being informed of the DMA memory write transaction by a CPU of the computer before initiation of the DMA memory write transaction, and to provide the indication to the CPU on request; and

to report to the first process that the first representation is overwritten by a DMA memory write transaction;

the DMA monitoring circuitry including

a plurality of registers outside the address space of the main memory, each register including an address tag and a vector of memory cells

control circuitry designed to establish an association between a one of the plurality of registers with a region of the memory when a modification to the region is detected by setting the address tag of the one register to an approximation of the address of the region, and to set the values of the memory cells of the vector to record a fine indication of the address of a memory location modified, the control circuitry being operable without continuing supervisory control of a CPU of the computer; and

circuitry designed to record indications of modification to pages of the main memory into the registers; and

read circuitry designed to respond to a read request from the CPU by providing an address of a modified memory location;

wherein the virtual memory management tables do not provide backing store for the modification indications stored in the registers.

2. A method, comprising the steps of:

monitoring DMA (direct memory access) memory write transactions of a computer by monitoring circuitry designed to record an indication of a memory location written by a DMA memory write transaction, the circuitry being designed to record the indication without being informed of the memory write transaction beforehand;

reading the indication from a CPU of the computer.

3. The method of claim 2, further comprising the steps of:

by a first process of a computer, generating a second representation in a computer memory of information stored in the memory in a first representation;

detecting when the first representation is overwritten by a DMA memory write transaction initiated by a second process, without the second process informing the first process of the DMA memory write transaction and without the first process examining the second process, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction.

4. The method of claim 2:

further comprising managing pages of a main memory divided into pages by a virtual memory manager, the manager using a table stored in the memory;

wherein the indication is recorded in a register from among a plurality of registers outside the address space of the main memory;

wherein the virtual memory management table does not provide backing store for the modification indications stored in the registers.

5. The method of claim 2, wherein the recorded indication records only the memory location, and not the datum written to the location.

6. The method of claim 2, further comprising the step of:

based at least in part by the indication value read by the CPU, erasing a cached datum.

7. The method of claim 2, wherein two DMA memory writes near each other in address and time generate only a single recorded indication of a write.

49. The method of claim 2, wherein:

the DMA monitoring circuitry is further designed to perform the monitoring and recording independently of circuitry and/or software for initiation or control of the monitored DMA memory write transactions.

8. Computer circuitry, comprising:

(direct memory access) monitoring circuitry designed to monitor DMA memory write transactions to a main memory of a computer by a DMA device of the computer and to record an indication of a location in the main memory written by the DMA memory write transaction, the DMA monitoring circuitry designed to operate without being informed of the DMA memory write transaction by a CPU of the computer before initiation of the DMA memory write transaction, and to provide the indication to the CPU on request.

9. The computer circuitry of claim 8, wherein the DMA monitoring circuitry further comprises:

a plurality of registers, each register including an address tag and a vector of memory cells;

control circuitry designed to establish an association between a one of the plurality of registers with a region of the memory when a modification to the region is detected by setting the register'"'"'s address tag of the to an address of the region, and to set the values of the memory cells of the vector to record an indication of a memory location modified, the control circuitry being operable without continuing supervisory control of a CPU of the computer; and

read circuitry designed to respond to a read request from the CPU by providing an address of a modified memory location.

10. The computer circuitry of claim 8:

wherein the CPU is designed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation; and

the DMA monitoring circuitry is further designed to detect when the first representation is overwritten by a DMA memory write transaction initiated by a second process, without the second process informing the first process of the DMA memory write transaction and without the first process examining the second process, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction.

11. The computer circuitry of claim 8, wherein the recorded indication of a location in the main memory indicates a physical address in the memory.

12. The computer circuitry of claim 8, further comprising a bit vector, a value of each bit of the bit vector designed to indicate whether a corresponding region in the main memory has been recently modified.

13. The computer circuitry of claim 8, further comprising matching circuitry to match an address of a memory modification to an address of a previously-stored indication of a previous nearby memory modification.

14. The computer circuitry of claim 8, wherein the recorded indication of a location in the main memory is initially recorded in an architecturally-visible location outside the main memory and outside a general register file of the computer.

15. The computer circuitry of claim 8, wherein the recorded indication of a location in the main memory is recorded, at least in part, based on a subdivision of the main memory into regions each consisting of a naturally-aligned block of pages of the memory.

16. The computer circuitry of claim 8, further comprising:

hardware and/or software designed to delete a cached datum, based at least in part on the indication provided to the CPU.

17. The computer circuitry of claim 8, further comprising:

I/O gateway circuitry between a system bus of the computer and the DMA device, the DMA monitoring circuitry being designed to monitor transactions on the I/O gateway circuitry.

18. The computer circuitry of claim 8, wherein the DMA monitoring circuitry is further designed to dismiss a content of the DMA monitoring circuitry as a side-effect of being read.

19. A method, comprising the steps of:

by a first process of a computer, generating a second representation in a computer memory of information stored in the memory in a first representation;

reporting to the first process that the first representation is overwritten by a DMA memory write transaction initiated by a second process, without the second process informing the first process of the DMA memory write transaction, the reporting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction.

20. The method of claim 19:

wherein the detection is recorded in a register from among a plurality of registers outside the address space of the main memory, pages of the main memory being divided into pages for management by a virtual memory manager, the manager using a table stored in the memory;

wherein the virtual memory management table does not provide backing store for the detections stored in the registers.

21. The method of claim 19, further comprising the step of:

deleting a cached datum based at least in part on the overwriting reporting.

22. A computer comprising:

a CPU programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation;

DMA monitoring circuitry designed to detect when the first representation is overwritten by a DMA (direct memory access) memory write transaction initiated by the second process, without the second process informing the first process of the DMA memory write transaction, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction.

23. The computer of claim 22, wherein:

the DMA monitoring circuitry is further designed to record an indication of a location in the main memory written by the DMA memory write transaction, the DMA monitoring circuitry designed to operate without being informed of the DMA memory write transaction before initiation of the DMA memory write transaction, and to provide the indication to the CPU on request.

24. The computer of claim 22, further comprising matching circuitry to match an address of a memory modification to an address of a previously-stored indication of a previous nearby memory modification.

25. The computer of claim 22, wherein a recorded indication of a detected overwriting is recorded, at least in part, based on a subdivision of the main memory into regions each consisting of a naturally-aligned block of pages of the memory.

26. A computer comprising:

a main memory divided into pages for management by a virtual memory manager, the manager programmed to manage the pages using a table stored in the memory;

a plurality of registers outside the address space of the main memory, and circuitry designed to record indications of modification to pages of the main memory into the registers;

wherein the virtual memory management tables do not provide backing store for the modification indications stored in the registers.

27. The computer of claim 26, wherein the indication recording circuitry is based, at least in part, on a subdivision of the main memory into regions each consisting of a naturally-aligned block of pages.

28. The computer of claim 26, further comprising:

hardware and/or software designed to delete a cached datum based on the record of modifications.

29. The computer circuitry of claim 26, further comprising:

I/O gateway circuitry between a system bus of the computer and a DMA device; and

DMA monitoring circuitry designed to monitor transactions on the I/O gateway circuitry and record the modification indications into the registers.

30. The computer circuitry of claim 26, wherein the registers and recording circuitry create only a single record indication of two DMA memory writes near each other in address and time.

31. A method, comprising the steps of:

monitoring modifications to the contents of a main memory of a computer, and

on detection of a modification, writing into an address tag of one of a plurality of registers an approximation of the address of the modification, and writing into a memory cell of a plurality of cells of the register a fine indication of the address of the modification; and

providing the fine indication of the address of the modification to a CPU of the computer through a read request from the CPU.

32. The method of claim 31:

wherein the modifications are memory write transactions to memory by a DMA device of the computer, and the modifications are recorded as an indication of a memory location written by a DMA memory write transaction without being informed of the DMA memory write transaction by the CPU beforehand, the indication being readable by the CPU.

33. The method of claim 31, wherein the address of the modification stored in the address tag is a physical memory address.

34. The method of claim 31, wherein the vector of memory cells comprises a bit vector, a value of each bit of the bit vector designed to indicate whether a corresponding region in the main memory has been recently modified.

35. The method of claim 31, wherein the address tag comprises a content-addressable memory.

36. The method of claim 31, further comprising the step of:

deleting a cached datum, based at least in part on the providing.

37. The method of claim 31, further comprising the steps of:

associating a one of the plurality of registers with an address range by writing an address into the address tag of the one register; and

later, associating the one register with a different address range by writing a different address into the address tag of the one register.

38. The method of claim 31, further comprising the step of:

dismissing a content of the memory cell as a side-effect of reading the memory cells.

39. Computer circuitry, comprising:

a plurality of registers, each register including an address tag and a vector of memory cells;

control circuitry designed to establish an association between a one of the plurality of registers with a region of the memory when a modification to the region is detected by setting the address tag of the one register to an address of the region, and to set the values of the memory cells of the vector to record an indication of a memory location modified, the control circuitry being operable without continuing supervisory control of a CPU of the computer; and

read circuitry designed to respond to a read request from the CPU by providing an address of a modified memory location.

40. The computer circuitry of claim 39, further comprising:

a main memory divided into pages for management by a virtual memory manager, the manager managing the pages using a table stored in the memory;

circuitry designed to record indications of modification to pages of the main memory into the registers;

wherein the virtual memory management tables do not provide backing store for the modification indications stored in the registers.

41. The computer circuitry of claim 39, wherein an address stored in the address tag is a physical memory address.

42. The computer circuitry of claim 39, wherein the vector of memory cells comprises a bit vector, a value of each bit of the bit vector designed to indicate whether a corresponding region in the main memory has been recently modified.

43. The computer circuitry of claim 39, wherein the address tag comprises a content-addressable memory.

44. The compute circuitry of claim 39, wherein the regions are regions of a partition of the main memory into naturally-aligned block of pages of the memory.

45. The computer circuitry of claim 39, further comprising:

hardware and/or software designed to delete a cached datum based at least in part on the address of a modified memory location provided by the read circuitry.

46. The computer circuitry of claim 39, further comprising:

I/O gateway circuitry between a system bus of the computer and the DMA device; and

DMA monitoring circuitry designed to monitor transactions on the I/O gateway circuitry and record the modification indications into the registers.

47. The computer circuitry of claim 39, wherein the read circuitry is further designed to dismiss the content of one of the registers during a read request from the CPU.

48. The computer circuitry of claim 39:

wherein the modifications to memory include DMA memory write transactions for writing data to a main memory of a computer by a DMA device of the computer;

and further comprising circuitry and/or software designed to monitor DMA (direct memory access) memory write transactions, and designed to record an indication of a location in the main memory written by the DMA memory write transaction, and to provide the recorded indication to the CPU on request of the read circuitry;

the DMA monitoring circuitry/software being designed to perform the monitoring and recording independently of circuitry and/or software for initiation or control of the monitored DMA transactions.

50. A method, comprising the steps of:

monitoring DMA (direct memory access) memory write transactions, and recording an indication of a location in a main memory written by the DMA memory write transaction, the monitored DMA memory write transactions being writes to a main memory of a computer by a DMA device of the computer, circuitry and/or software for the monitoring and recording being designed to perform the monitoring and recording independently of circuitry and/or software for initiation or control of the monitored DMA transactions; and

at the request of a CPU of the computer, providing the indication to the CPU.

51. The method of claim 50, further comprising the steps of:

by a first process of a computer, generating a second representation in a computer memory of information stored in the main memory in a first representation;

detecting when the first representation is overwritten by a DMA memory write transaction initiated by a second process, without the second process informing the first process of the DMA memory write transaction and without the first process examining the second process, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction.

52. The method of claim 50, wherein the recorded indication of a location in the main memory is initially recorded in an architecturally-visible location outside the main memory and outside a general register file of the computer.

53. The method of claim 50, wherein an address tag for indicating the location in the main memory comprises a content-addressable memory.

54. The method of claim 50, wherein the recorded indication records only the memory location, and not the datum written to the location.

55. An apparatus, comprising:

circuitry and/or software designed to monitor DMA (direct memory access) memory write transactions, and designed to record an indication of a location in the main memory written by the DMA memory write transaction, and to provide the recorded indication to the CPU on request;

the monitored DMA memory write transactions being writes to a main memory of a computer by a DMA device of the computer;

the DMA monitoring circuitry/software being designed to perform the monitoring and recording independently of circuitry and/or software for initiation or control of the monitored DMA transactions.

56. The apparatus of claim 55, wherein:

the DMA monitoring circuitry/software is further designed to operate without being informed of the DMA memory write transaction by a CPU of the computer before initiation of the DMA memory write transaction.

57. The apparatus of claim 55:

the main memory is divided into pages for management by a virtual memory manager, the manager programmed to manage the pages using a table stored in the memory;

and further comprising a plurality of registers outside the address space of the main memory, and circuitry designed to record the locations, being pages, in the main memory written by the DMA memory write transactions, into the registers;

wherein the virtual memory management tables do not provide backing store for the location indications stored in the registers.

58. The apparatus of claim 55, wherein the recorded indication of a location in the main memory indicates a physical address in the main memory.

59. The apparatus of claim 55, further comprising:

circuitry and/or software designed to erase a cached datum based at least in part on the recorded indication provided to the CPU.

60. The apparatus of claim 55, wherein the DMA monitoring circuitry/software being designed to generate only a single indication of a location written when two DMA memory writes near each other in time write to locations near each other in address.