Dynamic variable page size translation of addresses

• US 6,549,997 B2
• Filed: 03/16/2001
• Issued: 04/15/2003
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kalyanasundharam, Vydhyanathan
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/810,816
• Publication Number:
  US 20020133685A1
• Time in Patent Office: 760 Days
• Field of Search: 711/207
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/652 Page size control

Abstract

The current disclosure concerns dynamic variable page size translation of addresses. Such translation can be achieved at higher clock speeds than have heretofore been possible due to the use of a translation lookaside buffer (TLB) with RAM cells which eliminate the need to utilize circuitry external to the TLB. Such translation can also be bypassed at higher speeds than have heretofore been possible due to the use of translation bypass circuitry which eliminates the need to utilize circuitry external to the TLB.

Claims

1. A translation look-aside buffer for translating received virtual addresses into physical addresses in a variable page size memory having N page sizes wherein N is an integer greater than 1, the translation look-aside buffer comprising:

a content addressable memory for storing virtual address tags and for matching the received virtual addresses to the address tags to thereby generate CAM match signals each referencing a page table entry; and

plural page table entries coupled to the content addressable memory for targeted action based on the CAM match signal, each page table entry storing physical address data corresponding to respective virtual address data and comprising;

a plurality of first-type memory cells grouped into N−

1 cell groups, each first-type memory cell storing a single physical address bit; and

N−

1 second-type memory cells, each second-type memory cell coupled to a cell group and storing size-field data associated with the coupled cell group, the physical address data stored in the coupled cell group being output responsive to the size-field data is in a first state, and received virtual address bits corresponding to the coupled cell group being output responsive to the size-field data is in a second state.

2. The translation look-aside buffer of claim 1, wherein the content addressable memory generates a match signal responsive to a virtual address matching a virtual address tag and wherein each first-type memory cell comprises:

a physical address latch for storing the single physical address bit; and

a multiplexer coupled to the physical address latch and including at least a first and a second multiplexer input, a select-signal input, and a multiplexer output, the first multiplexer input receiving the physical address bit from the physical address latch, the second multiplexer input receiving a single bit of the virtual address, and the select-signal input receiving the size-field data from the associated second-type memory cell, the multiplexer outputting the single physical address bit responsive to the size-field data is in the first state, and the multiplexer outputting the single virtual address bit responsive to the size-field data is in the second state.

3. The translation look-aside buffer of claim 1, wherein each second-type memory cell comprises:

a size-field data latch for storing the size-field data; and

output circuitry directly coupled to a respective first-type memory cell for outputting the size-field data from the second-type memory cell directly into the coupled memory cell group.

4. The translation look-aside buffer of claim 1, wherein N equals 4.

5. A translation look-aside buffer for translating virtual addresses comprised of virtual address bits into physical addresses, the translation look-aside buffer comprising:

a content addressable memory for storing virtual address tags corresponding to the virtual addresses; and

a page table entry array coupled to the content addressable memory and receiving the virtual addresses, the page table entry array including a plurality of page table entries for storing physical addresses corresponding to respective ones of the virtual addresses tags, each page table entry comprising;

a physical address cell group, each physical address cell in the cell group storing a single physical address bit; and

a size-field memory cell coupled to the cell group and storing size-field data associated with the cell group,

the page table entry array outputting the physical address bits stored in the cell group responsive to the size-field data is in a first state, and the page table entry array outputting the virtual address bits responsive to the size-field data is in a second state.

6. The translation look-aside buffer of claim 5, wherein each physical address cell comprises:

a physical address latch storing the physical address bit; and

a multiplexer coupled to the physical address latch, the multiplexer receiving the physical address bit from the physical address latch, the virtual address bit, and the size-field data from the size-field cell, the multiplexer outputting the physical address bit responsive to the size-field data is in the first state and outputting the virtual address bit responsive to the size-field data is in the second state.

7. The translation look-aside buffer of claim 6, wherein each size-field memory cell comprises:

a size-field data latch storing the size-field data; and

means for coupling the size-field data latch to the multiplexer of the physical address cell such that data from the size-field latch is directly fed into the multiplexer.

8. The translation look-aside buffer of claim 6, wherein each size-field memory cell comprises:

a size-field data latch storing the size-field data; and

means for directly coupling the data latch to the multiplexer of the physical address cell coupled thereto such that data from the size-field memory cell is directly fed into the multiplexer of the coupled physical address cell.

9. A method of using a translation look-aside buffer to translate received virtual address data into physical address data, the translation look-aside buffer comprising at least one page table entry having at least one two-state size-field cell with size-field data stored therein and at least one physical address cell group with physical address data stored therein and directly coupled to the size-field cell, the method comprising:

receiving, at the page table entry, virtual address data corresponding to the physical address data stored in the cell group;

reading the size-field data stored in the size-field cell;

selecting, as an output from the page table entry and as part of the translated physical address data, the physical address data stored in the cell group responsive to the size-field cell is in a first state; and

selecting, as an output from the page table entry and as part of the translated physical address data, the received virtual address data responsive to the size-field is in a second state.

10. The method of claim 9 further comprising:

the page table entry bypassing the steps of selecting the physical address data and selecting the received virtual address data to thereby select the virtual address data in response to receipt of a translation bypass signal.

11. A translation look-aside buffer of a variable page size memory having a plurality of page sizes for translating received virtual address data into translated physical address data, the translation look-aside buffer comprising:

a content addressable memory comprising a plurality of memory cells for storing virtual address tags corresponding to the received virtual address data, the content addressable memory generating a match signal referencing a page table entry which corresponds to one of the stored virtual address tags; and

a page table entry array coupled to the content addressable memory and including a plurality of page table entries which each store physical address data, the array being capable of receiving a generated match signal and identifying a unique page table entry referenced by the match signal, each page table entry comprising;

a plurality of first-type memory cell groups, each cell group comprising a plurality of first-type memory cells and each first-type memory cell storing one physical address bit; and

a plurality of second-type memory cells, each second-type memory cell coupled to a first-type cell group and storing size-field data associated with the coupled cell group, the physical address data stored in the coupled cell group being output responsive to the size-field data is in a first state, and the received virtual address data corresponding to the coupled cell group being output responsive to the size-field data is in a second state.

12. The translation look-aside buffer of claim 11, further comprising translation bypass circuitry for preventing selection of the physical address data in response to a translation bypass signal.

13. A memory cell for a translation look-aside buffer which receives virtual address data corresponding to physical address data, stores size field data indicative of the page size of a memory and generates a read signal, the memory cell comprising:

a physical address latch for storing a single physical address bit of the physical address;

a multiplexer coupled to the physical address latch, the multiplexer comprising at least a first and second multiplexer inputs, a select-signal input and a multiplexer output, the first input receiving the address bit from the physical address latch, the second input receiving a virtual address bit of the received virtual address data, and the select-signal input receiving the size-field data, the multiplexer outputting the physical address bit responsive to the size-field data is in a first state and outputting the virtual address bit responsive to the size-field data is in a second state; and

dynamic read circuitry coupled to the multiplexer for outputting from the memory cell the multiplexer output in response to the read signal.

14. A dynamic variable page size translation look-aside buffer for translating virtual addresses into physical addresses in a variable page size memory having a plurality of page sizes, the translation look-aside buffer comprising:

means for storing virtual address tags which correlate the virtual addresses to the physical addresses; and

means for storing page table entries coupled to the means for storing virtual address tags, each page table entry corresponding to one of the virtual address tags and storing a physical address, each page table entry comprising;

a plurality of physical address memory cell groups, each cell group including at least one cell and storing physical address data;

a plurality size-field memory cells coupled to respective ones of the physical address cell groups and storing size-field data for respective ones of the cell groups;

means for outputting the physical address data of a particular cell group when the data stored in the size-field cell which is coupled to the particular cell group is in a first state;

means for outputting virtual address data corresponding to the physical address data of a particular cell group when data stored in the size-field cell which is coupled to the particular cell group is in a second state.

15. The translation look-aside buffer of claim 14, wherein

the means for storing virtual address tags generates a match signal responsive to a virtual address matching one of the virtual address tags; and

each physical address memory cell comprises;

a physical address storing means for storing a physical address bit;

multiplexer means for receiving (a) the physical address bit from the physical address storing means, (b) a virtual address bit, and (c) the size-field data from the coupled size-field memory cell and for outputting the physical address bit responsive to the size-field data is in the first state and the virtual address bit responsive to the size-field data is in the second state; and

dynamic read means coupled to the multiplexer means and the means for storing virtual address tags, the read means outputting the output of the multiplexer means in response to a match signal from the means for storing the virtual address tags.

16. The translation look-aside buffer of claim 14, wherein each size-field memory cell comprises:

size-field storing means for storing size-field data; and

means for outputting the size-field data directly into the coupled cell group.

17. A method of managing data in a translation look-aside buffer of a variable page size memory using virtual addresses corresponding to physical addresses, the virtual memory having N page sizes wherein N is an integer greater than 1 and each of the virtual addresses comprising a plurality of virtual address bits, the method comprising:

storing physical address data, the physical address data grouped into N−

1 groups and each group comprising a plurality of physical address bits;

storing N−

1 size-field data coupled to the respective N−

1 groups, each of the size-field data being stored in a first state when the physical address bits in the coupled group will be used to generate the physical address and the size-field data being stored in a second state when the virtual address bits corresponding to the coupled group will be used to generate the physical address;

responsive to a data request which includes the virtual address, outputting a translated physical address that corresponds to the virtual address, comprising;

outputting the physical address bits stored in the coupled cell group responsive to the size-field is in the first state; and

outputting the virtual address bits corresponding to the coupled cell group responsive to the size-field is in the second state.

18. A method of managing data in a translation look-aside buffer of a variable page size virtual memory using virtual addresses corresponding to physical addresses, the virtual memory having N page sizes wherein N is an integer greater than 1 and each of the virtual addresses comprising a plurality of virtual address bits, the method comprising:

storing physical address data, the physical address data grouped into N−

1 groups and each group comprising a plurality of physical address bits; and

storing N−

1 size-field data coupled to the respective N−

1 groups, each of the size-field data being stored in a first state when the physical address bits in the coupled group will be used to generate the physical address and the size-field data being stored in a second state when the virtual address bits corresponding to the coupled group will be used to generate the physical address.

19. A method of using a translation look-aside buffer to translate received virtual addresses into translated physical addresses during a single two-phase timing cycle, the translation look-aside buffer comprising a content addressable memory and a page table entry array with a plurality of page table entries coupled to the content addressable memory, each page table entry comprising at least one physical address cell group for storing physical address data potentially corresponding to a received virtual address, each page table entry further comprising at least one two-state size-field cell coupled to the cell group, the method comprising:

during the first phase of the timing cycle;

receiving a virtual address at both the content addressable memory and the page table entry array;

using the content addressable memory to convert the received virtual address into a match signal which references one of the page table entries in the array; and

using the virtual address to precharge the physical address cell group of at least one page table entry; and

during the second phase of the timing cycle;

receiving the match signal at the page table entry array;

outputting, as a portion of the translated physical address, the physical address data from the cell group of the page table entry referenced by the match signal responsive to the coupled size-field cell is in a first state; and

outputting, as a portion of the translated physical address, the received virtual address data corresponding to the physical address data stored in the cell group of the page table entry referenced by the match signal responsive to the size-field cell is in a second state.

20. The method of claim 19 wherein

each physical address cell of each cell group comprises a latch for storing a single physical address bit and a multiplexer coupled to the latch;

the step of outputting the physical address data further comprises receiving the physical address bit and a single bit of the virtual address and selecting as the cell output the physical address bit responsive to the size-field cell being in the first state; and

the step of outputting the physical address data further comprises receiving the physical address bit and a single bit of the virtual address selecting the virtual address bit as the cell output responsive to the size-field cell being in the second state.