Fully integrated process for MIM capacitors using atomic layer deposition

• US 6,551,399 B1
• Filed: 01/10/2000
• Issued: 04/22/2003
• Est. Priority Date: 01/10/2000
• Status: Expired due to Fees

• Current Assignee: Aixtron Inc. (Aixtron AG)
• Original Assignee: Genus PLC
• Inventors: Sneh, Ofer, Seidel, Thomas E.
• Primary Examiner(s): KUNEMUND, ROBERT M
• Application Number:
  US09/480,804
• Time in Patent Office: 1,198 Days
• Field of Search: 117/102, 117/103, 117/106, 117/89
• US Class Current: 117/102
• CPC Class Codes: C23C 16/0236 by etching with a reactive gas
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: C23C 16/45561 Gas plumbing upstream of the reaction chamber
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02222 the compound being a silazane
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31616 Deposition of Al2O3
• CPC Class Codes: H01L 21/31637 Deposition of Tantalum oxides, e.g. Ta2O5
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A method and apparatus for fabricating a metal-insulator-metal capacitor by performing atomic layer deposition (ALD). A fully integrated process flow prevents electrode-dielectric contamination during an essential ex situ bottom electrode patterning step.

Claims

1. A method of fabricating a metal-insulator-metal capacitor comprising:

depositing a bottom conductive layer by atomic layer deposition;

depositing a sacrificial layer, which is not a photoresist, above the bottom conductive layer by atomic layer deposition without exposing the bottom conductive layer to an ambient environment;

exposing the sacrificial layer to an oxidizing ambient to undergo a photolithographic and etching processes that form a defined stacked structure by pattern delineating the bottom conductive and sacrificial layers;

removing the sacrificial layer to expose the underlying bottom conductive layer without exposing the bottom conductive layer to the ambient environment;

depositing a dielectric layer over the exposed bottom conductive layer by atomic layer deposition without exposing the bottom conductive layer to the ambient environment;

depositing a top conductive layer over the dielectric layer without exposing the underlying dielectric layer to the ambient environment; and

forming the top conductive layer over the defined stacked structure.

2. The method of claim 1 wherein the depositing of the top conductive layer includes depositing the top conductive layer by atomic layer deposition.

3. The method of claim 1 wherein the depositing of the top conductive layer includes depositing the top conductive layer by chemical vapor deposition.

4. The method of claim 1 wherein the depositing of the top conductive layers includes depositing the top conductive layer by plasma-enhanced chemical vapor deposition.

5. A method of fabricating a metal-insulator-metal capacitor comprising:

depositing a bottom metal layer by atomic layer deposition;

depositing a sacrificial layer comprised of metal above the bottom metal layer by atomic layer deposition without exposing the bottom metal layer to an ambient environment;

exposing the sacrificial layer to an oxidizing ambient to undergo a photolithographic and etching processes that form a defined stacked structure by pattern delineating the bottom metal and sacrificial layers;

removing the sacrificial layer to expose the underlying bottom metal layer by selective etch without exposing the bottom metal layer to the ambient environment and without etching the underlying bottom metal layer;

depositing a dielectric layer over the exposed bottom metal layer by atomic layer deposition without exposing the bottom metal layer to the ambient environment;

depositing a top metal layer over the dielectric layer without exposing the underlying dielectric layer to the ambient environment; and

forming the top metal layer over the defined stacked structure.

6. The method of claim 5 further comprising pretreating a surface underlying the bottom metal layer to make the surface reactive to atomic layer deposition of the bottom metal layer.

7. The method of claim 5 further comprising depositing an adhesion layer prior to depositing the bottom metal layer, the adhesion layer being deposited by atomic layer deposition.

8. The method of claim 5 further comprising pretreating the bottom metal layer after removal of the sacrificial layer to make the bottom metal layer reactive to atomic layer deposition of the dielectric layer.

9. The method of claim 5 further comprising pretreating the dielectric layer to make the dielectric layer reactive to the depositing of the top metal layer.

10. The method of claim 5 further comprising pretreating a substrate surface to make the substrate surface reactive to atomic layer deposition of an adhesion layer and depositing the adhesion layer prior to depositing the bottom metal layer, the adhesion layer being deposited by atomic layer deposition.

11. The method of claim 10 further comprising pretreating the bottom metal layer after removal of the sacrificial layer to make the bottom metal layer reactive to atomic layer deposition of the dielectric layer.

12. The method of claim 11 further comprising pretreating the dielectric layer to make the dielectric layer reactive to the depositing of the top metal layer.