Three dimensional structure integrated circuits

• US 6,551,857 B2
• Filed: 02/06/2001
• Issued: 04/22/2003
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/776,885
• Publication Number:
  US 20010033030A1
• Time in Patent Office: 805 Days
• Field of Search: 438/106, 438/107, 438/108, 438/109, 438/618, 438/622, 438/637, 365/51, 365/63
• US Class Current: 438/109
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A method of using integrated circuitry having a data source formed in one layer of semiconductor material, a data sink formed in another layer of semiconductor material, and interconnect circuitry formed within a volume within which the first and second layers of semiconductor material overlie one another, the method comprising:

exchanging control signals between the data sink and the data source; and

transferring many data bytes between the data source and the data sink simultaneously.

2. The method of claim 1, wherein the semiconductor material is one of single crystal semiconductor material and polycrystalline semiconductor material.

3. The method of claim 1, wherein the data source is formed using a different process technology than the data sink, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

4. The method of claim 1, wherein the data sink comprises a microprocessor.

5. The method of claim 1, wherein the data source comprises at least one memory layer and the integrated circuitry comprises at least one logic layer, further comprising the at least one logic layer performing testing of the at least one memory layer.

6. The method of claim 1, wherein the data source comprises at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

7. The method of claim 1, wherein the data source comprises at least one memory layer and the integrated circuit comprises at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

8. The method of claim 1, wherein at least one of the data source and the data sink is formed in a plurality of layers of semiconductor material.

9. A method of making integrated circuitry, comprising:

forming a data source in one layer of semiconductor material;

forming a data sink in another layer of semiconductor material, there being a volume within which the first and second layers of semiconductor material overlie one another; and

within said volume, forming interconnect circuitry whereby many data bytes are transferred between the data source and the data sink simultaneously.

10. The method of claim 9, wherein the semiconductor material is one of single crystal semiconductor material and polycrystalline semiconductor material.

11. The method of claim 9, wherein the semiconductor material is one of single crystal semiconductor material and polycrystalline semiconductor material.

12. The method of claim 9, wherein the data source is formed using a different process technology than the data sink, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

13. The method of claim 9, wherein the data sink comprises a microprocessor.

14. The method of claim 9, wherein the data source comprises at least one memory layer and the integrated circuitry comprises at least one logic layer, further comprising the at least one logic layer performing testing of the at least one memory layer.

15. The method of claim 9, wherein the data source comprises at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

16. The method of claim 9, wherein the data source comprises at least one memory layer and the integrated circuit comprises at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

17. The method of claim 9, wherein at least one of the data source and the data sink is formed in a plurality of layers of semiconductor material.

18. A method of information processing using a stacked integrated circuit having multiple stacked integrated circuit layers, the method comprising:

transferring information between any two of the stacked integrated circuit layers during which many bytes of data are transferred;

wherein the transfer of information occurs through vertical interconnections interior to the stacked integrated circuits.

19. The method of claim 18, wherein the stacked integrated circuit layers are formed of one of single crystal semiconductor material and polycrystalline semiconductor material.

20. The method of claim 18, wherein one stacked integrated circuit layer is formed using a different process technology than another stacked integrated circuit layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

21. The method of claim 18, wherein at least one of the stacked integrated circuit layers comprises a microprocessor.

22. The method of claim 18, wherein the multiple stacked integrated circuit layers include at least one memory layer and at least one logic layer, further comprising the at least one logic layer performing testing of the at least one memory layer.

23. The method of claim 18, wherein the multiple stacked integrated circuit layers include at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

24. The method of claim 18, wherein the multiple stacked integrated circuit layers include at least one memory layer and at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

25. The method of claim 18, wherein the stacked integrated circuit comprises a data source and a data sink, wherein at least one of the data source and the data sink is formed in a plurality of layers of semiconductor material.

26. A method of making integrated circuitry comprising:

providing a first integrated circuit having a thickness Th₁ and a second integrated circuit having a thickness Th₂; and

forming a large number of short interconnect segments interconnecting the first and second integrated circuits;

wherein the interconnect segments have lengths of about Th₁+Th₂ or less.

27. The method of claim 26, wherein the interconnect segments traverse at least one of the first thickness and the second thickness.

28. The method of claim 26, wherein forming an interconnect segment comprises forming a conductive land on a surface of the first integrated circuit and forming a conductive land on a surface of the second integrated circuit.

29. The method of claim 26, wherein forming an interconnect segment comprises forming a conductive land on a surface of the first integrated circuit, forming a conductive land on a surface of the second integrated circuit, and forming a via formed within one of the first and second integrated circuits.

30. The method of claim 29, further comprising bonding together the conductive land formed on the surface of the first integrated circuit and the conductive land formed on the surface of the second integrated circuit.

31. The method of claim 29, further comprising bonding together the conductive land formed on the surface of the first integrated circuit and the conductive land formed on the surface of the second integrated circuit by thermal diffusion bonding.

32. The method of claim 26, further comprising grouping the interconnect segments to form a dense interconnect array.

33. The method of claim 26, wherein the first integrated circuit and the second integrated circuit are formed of one of single crystal semiconductor material and polycrystalline semiconductor material.

34. The method of claim 26, wherein one of the first and second integrated circuits is formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

35. The method of claim 26, wherein at least one of the first and second integrated circuits includes a microprocessor.

36. The method of claim 26, wherein the integrated circuitry includes one or more further integrated circuits, the integrated circuits including a plurality of memory layers and at least one logic layer, wherein the at least one logic layer performs testing of at least one of the memory layers.

37. The method of claim 26, wherein the integrated circuits include at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

38. The method of claim 26, wherein the integrated circuits include at least one memory layer and at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

39. The method of claim 26, wherein the integrated circuitry comprises a data source and a data sink, wherein at least one of the data source and the data sink is formed in a plurality of layers of semiconductor material.

40. A method of using integrated circuitry having a data source formed in one circuit layer, a data sink formed in another circuit layer, and interconnect circuitry formed within a volume within which the first and second circuit layers overlie one another, the method comprising:

exchanging control signals between the data sink and the data source and simultaneously transferring many data bytes between the data source and data sink.

41. The method of claim 40, wherein the circuit layers are formed of one of single crystal semiconductor material and polycrystalline semiconductor material.

42. The method of claim 40, wherein the data source is formed using a different process technology than the data sink, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

43. The method of claim 40, wherein the data sink comprises a microprocessor.

44. The method of claim 40, wherein the data source comprises at least one memory layer and the integrated circuitry comprises at least one logic layer, further comprising the at least one logic layer performing testing of the at least one memory layer.

45. The method of claim 40, wherein the data source comprises at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

46. The method of claim 40, wherein the data source comprises at least one memory layer and the integrated circuit comprises at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

47. The method of claim 40, wherein at least one of the data source and the data sink is formed in a plurality of layers of semiconductor material.

48. A method of making integrated circuitry, comprising:

forming a data source in one circuit layer;

forming a data sink in another circuit layer, there being a volume within which the first and second circuit layers overlie one another; and

within said volume, forming interconnect circuitry whereby many data bytes are simultaneously transferred between the data source and data sink.

49. The method of claim 48, wherein the one circuit layer and the other circuit layer are formed of one of single crystal semiconductor material and polycrystalline semiconductor material.

50. The method of claim 48, wherein the data source is formed using a different process technology than the data sink, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

51. The method of claim 48, wherein the data sink comprises a microprocessor.

52. The method of claim 48, wherein the data source comprises a plurality of memory layers and the integrated circuitry comprises at least one logic layer, further comprising the at least one logic layer performing testing of at least one of the memory layers.

53. The method of claim 48, wherein the data source comprises at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

54. The method of claim 48, wherein the data source comprises at least one memory layer and the integrated circuitry comprises at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

55. The method of claim 48, wherein at least one of the data source and the data sink is formed in a plurality of layers of semiconductor material.

56. A method of making integrated circuitry comprising:

providing a first integrated circuit layer having a thickness Th1;

providing a second integrated circuit layer having a thickness Th2; and

forming a plurality of short interconnect segments interconnecting the first and second integrated circuit layers;

wherein the interconnect segments have lengths of about Th1+Th2 or less.

57. The method of claim 56, wherein the first integrated circuit layer and the second integrated circuit layer are formed of one of single crystal semiconductor material and polycrystalline semiconductor material.

58. The method of claim 56, wherein one of the first and second integrated circuit layers is formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

59. The method of claim 56, wherein at least one of the first and second integrated circuit layers includes a microprocessor.

60. The method of claim 56, wherein the circuitry includes at least one memory layer and at least one logic layer, wherein the at least one logic layer performs testing of the at least one memory layer.

61. The method of claim 56, wherein the circuitry includes at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

62. The method of claim 56, wherein the circuitry includes at least one memory layer and at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

63. The method of claim 56, wherein the circuitry includes a data source and a data sink, wherein at least one of the data source and the data sink is formed in a plurality of layers of semiconductor material.

64. A method of information processing using a stacked integrated circuit memory including at least one logic layer and at least one of memory layer, the method comprising:

initiating a memory access; and

during the memory access, routing data vertically through a plurality of connections interior to the stacked integrated circuit memory and between the at least one logic layer and at least one memory location on the at least one memory layer.

65. The method of claim 64 comprising the further step, during simultaneous and independent memory accesses, of accessing data from multiple memory locations on the at least one memory layer.

66. The method of claim 65, wherein data from a memory location of the multiple memory locations is used to perform ECC processing with respect to data from another memory location.

67. The method of claim 64, wherein data from memory locations on a second memory layer is used instead of data from defective memory locations on a first memory layer.

68. The method of claim 64, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

69. The method of claim 64 comprising the further steps of:

receiving within the at least one logic layer data from memory locations; and

for each memory location, distinguishing between at least four voltage levels to produce at least two bits of data.

70. The method of claim 64 comprising the further steps of:

receiving data within the at least one logic layer; and

decompressing the data.

71. The method of claim 64 comprising the further steps of:

compressing data within the at least one logic layer; and

writing the data to memory locations.

72. The method of claim 64, wherein the at least one logic layer includes memory circuitry and logic for performing at least some control functions on the memory circuitry.

73. The method of claim 64, wherein the at least one memory layer includes some but not all logic for initiating the memory access.

74. The method of claim 64 comprising the further steps of:

receiving within the at least one logic layer a virtual address; and

translating the virtual address to a real address.

75. The method of claim 64 comprising the further steps of:

receiving within the at least one logic layer an indirect address; and

translating the indirect address to a real address.

76. The method of claim 64 comprising the further step of receiving within the at least one logic layer a content word and producing as an output signal an address of the content word within at least one content-addressable memory circuit in the at least one memory layer.

77. The method of claim 64 comprising the further step of performing one of audio encoding and audio decoding on said data, after the memory access, which comprises a read access.

78. The method of claim 64 comprising the further step of performing one of audio encoding and audio decoding on said data, prior to the memory access, which comprises a write access.

79. The method of claim 64 comprising the further step of performing one of video encoding and audio decoding on said data, after the memory access, which comprises a read access.

80. The method of claim 64 comprising the further step of performing one of video encoding and audio decoding on said data, prior to the memory access, which comprises a write access.

81. The method of claim 64 comprising the further step of performing recognition processing on said data, after the memory access, which comprises a read access.

82. The method of claim 64 comprising the further step of performing recognition processing on said data, prior to the memory access, which comprises a write access.

83. The method of claim 81, wherein said recognition processing is voice recognition processing.

84. The method of claim 81, wherein said recognition processing is handwriting recognition processing.

85. The method of claim 82, wherein said recognition processing is voice recognition processing.

86. The method of claim 82, wherein said recognition processing is handwriting recognition processing.

87. The method of claim 64 comprising the further step of performing power management functions within the at least one logic layer.

88. The method of claim 64 comprising the further step of performing graphic acceleration functions within the at least one logic layer.

89. The method of claim 64 comprising the further step of performing database functions within the at least one logic layer.

90. The method of claim 64, wherein the at least one logic layer contains a microprocessor.

91. A method of information processing using a stacked integrated circuit having multiple integrated circuit layers, the method comprising:

transferring information between any two of the stacked integrated circuit layers during which many bytes of data are transferred such that the transfer of information occurs through a plurality of vertical interconnections interior to the stacked integrated circuits.

92. The method of claim 91, wherein one of the integrated circuit layers is a memory controller layer and one is a memory layer.

93. The method of claim 92, wherein the memory layer is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

94. A method of information processing using a stacked integrated circuit memory including at least one logic layer and at least one memory layer, the method comprising:

initiating a memory access; and

during the memory access, routing data vertically between the at least one logic layer and selected storage locations within the at least one memory layer such that the routing occurs through a plurality of connections interior to the stacked integrated circuit memory, and during a single memory access cycle, many bytes of data are routed from the selected storage locations to the at least one logic layer.

95. The method of claim 94, wherein the at least one logic layer is a memory controller layer.

96. The method of claim 94, wherein the at least one memory layer is made from one of single crystal semiconductor material and polycrystalline semiconductor material.

97. The method of claim 94, comprising the further step of testing, with the at least one logic layer, the at least one memory layer for defective storage locations.

98. The method of claim 94, wherein the at least one logic layer and the at least one memory layer are formed of one of single crystal semiconductor material and polycrystalline semiconductor material.

99. The method of claim 94, wherein the at least one memory layer is formed using a different process technology than the at least one logic layer, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

100. The method of claim 94, wherein the at least one logic layer performs testing of the at least one memory layer.

101. The method of claim 94, wherein the at least one memory layer has multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

102. The method of claim 94, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

103. The method of claim 94, wherein the stacked integrated circuit comprises a data source and a data sink, at least one of the data source and the data sink being formed in a plurality of layers of semiconductor material.

104. A method of making a stacked integrated circuit comprising:

forming an integrated circuit stack by bonding together a first integrated circuit layer having a first metallization pattern and a second integrated circuit layer having a second metallization pattern matching the first metallization pattern, thereby forming electrical contact between the first and second metallization patterns; and

forming vias that extend through at least one of the first and second integrated circuit layers at locations interior to said at least one of the first and second integrated circuit layers, including thinning said at least one of the first and second integrated circuit layers, to enable electrical contact to be established between the vias and a third integrated circuit layer.

105. The method of claim 104, wherein the integrated circuit layers are formed of one of single crystal semiconductor material and polycrystalline semiconductor material.

106. The method of claim 104, wherein at least one of the integrated circuit layers is formed using a different process technology than at least one other of the integrated circuit layers, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

107. The method of claim 104, wherein at least one of the integrated circuit layers comprises a microprocessor.

108. The method of claim 104, wherein the integrated circuit layers comprise at least one memory layer and at least one logic layer, further comprising the at least one logic layer performing testing of the at least one memory layer.

109. The method of claim 104, wherein the integrated circuit layers comprise at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

110. A method of information processing using a stacked integrated circuit including at least two logic layers, the method comprising:

initiating a memory access; and

during the memory access, routing data vertically through a plurality of connections interior to the stacked integrated circuit and between one of the at least two logic layers and at least one memory location on the other of the at least two logic layers.

111. The method of claim 110 comprising the further step, during simultaneous and independent memory accesses, of accessing data from multiple memory locations on the other of the at least two logic layers.

112. The method of claim 111, wherein data from one memory location on the other of the at least two logic layers is used to perform ECC processing with respect to data from another memory location on the other of the at least two logic layers.

113. The method of claim 110 comprising the further steps of:

receiving data within a logic layer; and

decompressing the data.

114. The method of claim 110 comprising the further steps of:

compressing data within a logic layer; and

writing the data to memory locations on the other of the at least two logic layers.

115. The method of claim 110, comprising the further step of providing a logic layer including memory circuitry and logic to perform at least some functions on the memory circuitry.

116. The method of claim 110 comprising the further steps of:

receiving within one of the at least two logic layers a virtual address; and

translating the virtual address to a real address.

117. The method of claim 110 comprising the further steps of:

receiving within one of the at least two logic layers an indirect address; and

translating the indirect address to a real address.

118. The method of claim 110 comprising the further step of performing one of audio encoding and audio decoding on said data, after the memory access, which comprises a read access.

119. The method of claim 110 comprising the further step of performing one of audio encoding and audio decoding on said data, prior to the memory access, which comprises a write access.

120. The method of claim 110 comprising the further step of performing one of video encoding and audio decoding on said data, after the memory access, which comprises a read access.

121. The method of claim 110 comprising the further step of performing one of video encoding and audio decoding on said data, prior to the memory access, which comprises a write access.

122. The method of claim 110 comprising the further step of performing recognition processing on said data, after the memory access, which comprises a read access.

123. The method of claim 110 comprising the further step of performing recognition processing on said data, prior to the memory access, which comprises a write access.

124. The method of claim 122, wherein said recognition processing is voice recognition processing.

125. The method of claim 122, wherein said recognition processing is handwriting recognition processing.

126. The method of claim 123, wherein said recognition processing is voice recognition processing.

127. The method of claim 123, wherein said recognition processing is handwriting recognition processing.

128. The method of claim 110 comprising the further step of performing power management functions with one of the at least two logic layers.

129. The method of claim 110 comprising the further step of performing graphic acceleration functions with one of the at least two logic layers.

130. The method of claim 110 comprising the further step of performing database functions with one of the at least two logic layers.

131. The method of claim 110, wherein one of the at least two logic layers contains a microprocessor.