Mini flash process and circuit

• US 6,551,878 B2
• Filed: 01/09/2001
• Issued: 04/22/2003
• Est. Priority Date: 09/03/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Green, James E., Clampitt, Darwin A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US09/757,878
• Publication Number:
  US 20010001720A1
• Time in Patent Office: 833 Days
• Field of Search: 438/211, 438/258, 438/257, 438/264, 438/266, 438/620, 438/586
• US Class Current: 438/258
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for making reduced-size FLASH EEPROM memory circuits, and to the resulting memory circuit. An FET integrated circuit having two different gate oxide thicknesses deposited at a single step, where a portion of the thickness of the thicker oxide is formed, that oxide is removed from the area of the chip to have the thinner oxide, then the rest of the thicker oxide is grown during the time that the thinner oxide is grown on the area of the chip to have the thinner oxide. Layers for the floating gate stacks are deposited. Trenches are etched in a first, and then a second perpendicular direction, and the perpendicular sides of the stacks are covered with vertical-plane nitride layers in two separate operations. Tungsten word lines and bit contacts are deposited. Aluminum-copper lines are deposited on the bit lines.

Claims

1. A method for fabricating an electronic circuit comprising:

forming a first dielectric layer on a first chip area to be used for a first set of transistors, on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors;

substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area;

forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area;

substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and

forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area.

2. The method according to claim 1, wherein the first dielectric layer is thicker than the second dielectric layer, and wherein the first dielectric is a gate oxide for signal transistors, and the second dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.

3. The method according to claim 2, wherein the first chip area and the second chip area are substantially co-planar.

4. A method for fabricating an electronic circuit comprising:

forming a first dielectric layer on a first chip area to be used for a first set of transistors that are to be used for signalling, and on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors that are to be used for floating-gate memory;

substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; and

forming a second dielectric layer on the second chip area, while simultaneously thickening the dielectric of the first chip area,

substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and

forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area, wherein the third dielectric layer provides a gate oxide region sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing.

5. A method for fabricating an electronic circuit comprising:

forming a first dielectric layer on both a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors, and on a third chip area to be used for a third set of transistors, wherein the first dielectric layer is a gate oxide sufficiently thick to prevent electrical breakdown at operating voltages to be used for signalling;

removing the first dielectric layer from the second chip area but not from the first chip area; and

forming a second dielectric layer on the second chip area to be used for the second set of transistors, while simultaneously thickening the dielectric of the first chip area to be used for the first set of transistors,

substantially removing all dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and

forming a third dielectric layer on the second chip area, while thickening the dielectric of the first chip area and the dielectric layer on the second chip area, wherein the third dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing; and

covering the first dielectric layer and the second dielectric layer with a polysilicon layer that becomes a polysilicon transistor gate for transistors in the first chip area and becomes a polysilicon floating gate for transistors in the second chip area.

6. A method for fabricating an electronic circuit comprising:

forming a dielectric layer on a chip area of a substrate to be used for a set of transistors;

depositing a floating-gate poly layer over the dielectric layer;

depositing an inter-poly nitride layer over the floating-gate poly layer;

depositing a control-gate poly layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate poly layer;

removing material to form a plurality of stack rows separated by isolation trenches, each of the isolation trenches substantially parallel to a first direction, wherein the isolation trenches extend into the substrate;

depositing a nitride layer along at least side portions of the rows;

substantially filling the isolation trenches with an insulator;

removing material to form a plurality of columns separated by secondary trenches, each of the secondary trenches substantially perpendicular to the first direction, wherein the secondary trenches extend to the substrate; and

depositing a nitride layer along at least side portions of the rows.

7. A method for fabricating an electronic circuit comprising:

forming a dielectric layer on a chip area to be used for a set of transistors;

depositing a floating-gate poly layer over the dielectric layer;

depositing an inter-poly nitride layer over the floating-gate poly layer;

depositing a control-gate poly layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate poly layer;

etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer;

etching the stack to form a drain end and a source end;

depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench;

depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench;

depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

8. The method according claim 7, further comprising:

forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end;

forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and

forming a tungsten gate contact to substantially contact the WSix layer.

9. The method according claim 8, further comprising:

forming an aluminum-copper (AlCu) line substantially in contact with the tungsten drain contact.

10. A method for fabricating an electronic circuit comprising:

forming a dielectric layer on a chip area to be used for a set of transistors;

depositing a floating-gate poly layer over the dielectric layer;

depositing an inter-poly nitride layer over the floating-gate poly layer;

depositing a control-gate poly layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate poly layer;

etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer;

etching the stack to form a drain end and a source end;

depositing a nitride layer covering the first and second side from the inter-poly nitride layer to their respective trenches, and covering the drain end and source ends from the inter-poly nitride layer to the substrate;

forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end;

forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and

forming a tungsten gate contact to substantially contact the WSix layer.

11. A method for fabricating an electronic circuit, the circuit having a substrate and a floating-gate stack on the substrate, the stack including a gate oxide on the substrate, and at least one poly layer on the gate oxide, the method comprising:

etching a plurality of trenches through the stack, some of the trenches extending into the substrate, and others of the trenches stopping substantially at a top surface of the substrate; and

depositing a nitride spacer layer on sides of the trenches.

12. The method according claim 11, wherein the nitride spacer layer is deposited to isolate all sides of a floating gate poly layer.

13. The method according claim 11, wherein

the etching of the plurality of trenches comprises etching a first plurality of substantially parallel trenches through the stack into the substrate,

the depositing of the nitride spacer layer comprises depositing nitride on sides of the first plurality of parallel trenches,

the etching of the plurality of trenches further comprises etching a second plurality of substantially parallel trenches substantially perpendicular to the first plurality of substantially parallel trenches and

the depositing of the nitride spacer layer further comprises depositing nitride on sides of the second plurality of parallel trenches.

14. The method according claim 13, wherein the stack includes two poly layers separated by an inter-poly dielectric layer, and wherein the nitride spacer layer covers the sides of both poly layers and the sides of the inter-poly dielectric layer.

15. A method for fabricating an electronic circuit, the circuit having a substrate, a gate oxide on the substrate, a floating-gate poly layer on the gate oxide, an inter-poly nitride layer on the floating gate poly layer, a control-gate poly layer on the inter-poly nitride layer;

a tungsten-silicide (WSix) layer on the control-gate poly layer, and a nitride cap layer on the WSix layer;

the method comprising;

etching a plurality of isolation trenches along a first direction through the stack into the substrate;

depositing a nitride spacer layer on sides of the isolation trenches;

further etching to remove the nitride cap and to further deepen the plurality of isolation trenches into the substrate;

filling the isolation trenches with tetraethylorthosilicate (TEOS);

covering an area of the circuit with planarized borophosphosilicate glass (BPSG);

etching lines along a second direction substantially perpendicular to the isolation trenches;

depositing a nitride spacer layer on sides of the lines;

covering the area of the circuit with a thin TEOS layer;

covering the area of the circuit with planarized BPSG;

etching trenches through the TEOS layer between adjacent transistors to the substrate and on portions of adjacent transistor areas to the WSix layer, using an etch that does not substantially etch nitride;

depositing a titanium or titanium nitride barrier layer;

filling the trench with tungsten;

chemical-mechanical polishing (CMP) to planarize and remove tungsten and upper portions of oxide, stopping near tops of the nitride spacers;

covering with BPSG, etching contacts through contact areas, depositing barrier layer in the contact areas, depositing tungsten in the contact areas, and chemical-mechanical polishing (CMP) back the tungsten to leave only the tungsten in the contact areas; and

depositing aluminum copper (ALCU), etching interconnects, and covering with a passivation layer.

16. A method for fabricating an electronic circuit on a wafer comprising:

depositing a dielectric layer on a substrate of the wafer the dielectric layer having a first thickness in a first area of the circuit and a second thickness, thinner than the first thickness, in a second area of the circuit;

depositing a first poly gate layer over the dielectric layer;

depositing an inter-poly dielectric layer over the first poly layer;

removing the inter-poly dielectric from the first area but not from the second area; and

depositing a second poly gate layer over the inter-poly dielectric layer in the second area and on the first poly layer in the first area, wherein the second poly gate layer forms a control gate for a memory cell in the second area of the circuit.

17. The method according claim 16, further comprising:

depositing a tungsten-silicide (WSix) layer over the second poly gate layer to reduce contact resistance.

18. The method according claim 16, further comprising:

depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.

19. A method for fabricating an electronic circuit on a wafer comprising:

depositing a dielectric layer on a substrate of the wafer;

depositing a first poly gate layer over the dielectric layer;

depositing an inter-poly dielectric layer over the first poly layer;

depositing a second poly gate layer over the inter-poly dielectric layer;

removing the inter-poly dielectric and the second poly gate layer from some but not all of the first poly gate layer;

depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.

20. A method of fabricating an electronic circuit comprising:

forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors;

substantially removing the first dielectric layer from at least the second chip area while substantially leaving the first dielectric layer on the first chip area;

forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area;

substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and

forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area.

21. The method according to claim 20, wherein the first dielectric is a gate oxide for signal transistors, and the third dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.

22. The method according to claim 21, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer; and

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer.

23. The method according to claim 20, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer;

etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the third dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer;

etching the stack to form a drain end and a source end;

depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench;

depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench;

depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

24. The method according to claim 20, comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer;

etching trenches to define a floating-gate stack; and

depositing a nitride spacer layer on sides of the trenches to isolate all sides of the floating gate polysilicon layer.

25. A method of fabricating an electronic circuit comprising:

forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors;

substantially removing the first dielectric layer from at least the second chip area while substantially leaving the first dielectric layer on the first chip area;

forming a second dielectric layer on the second chip area, while simultaneously thickening the dielectric of the first chip area,

substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and

forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area;

wherein the third dielectric layer provides a gate oxide region sufficiently thin to allow Fowler-Nordheim tunneling for at least one of programming and erasing.

26. The method according to claim 25, wherein the first dielectric is a gate oxide for signal transistors, and the third dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.

27. The method according to claim 26, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer; and

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer.

28. The method according to claim 25, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer;

etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the third dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer;

etching the stack to form a drain end and a source end;

depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench;

depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench;

depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

29. The method according to claim 25, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer;

etching trenches to define a floating-gate stack; and

depositing a nitride spacer layer on sides of the trenches to isolate all sides of the floating gate polysilicon layer.

30. A method of fabricating an electronic circuit comprising:

forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors;

removing the first dielectric layer from the second chip area but not from the first chip area; and

forming a second dielectric layer on the second chip area to be used for the second set of transistors, while simultaneously thickening the dielectric of the first chip area to be used for the first set of transistors,

substantially removing any dielectric layer from the third chip area while substantially leaving the dielectric layer on the first chip area and the dielectric layer on the second chip area; and

forming a third dielectric layer on the third chip area, while thickening the dielectric of the first chip area and the dielectric layer of the second chip area;

wherein the third dielectric layer is a gate oxide sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing; and

covering the first dielectric layer and the third dielectric layer with a polysilicon layer that becomes a polysilicon transistor gate for transistors in the first chip area and becomes a polysilicon floating gate for transistors in the third chip area.

31. The method according to claim 30, wherein the first dielectric is a gate oxide for signal transistors, and the third dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors.

32. The method according to claim 31, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer; and

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer.

33. The method according to claim 30, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer;

etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the third dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer;

etching the stack to form a drain end and a source end;

depositing a nitride layer covering the first side from the inter-poly nitride layer to the first trench;

depositing a nitride layer covering the second side from the inter-poly nitride layer to the second trench;

depositing a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

depositing a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

34. The method according to claim 30, further comprising:

depositing a floating-gate polysilicon layer over the third dielectric layer;

depositing an inter-poly nitride layer over the floating-gate polysilicon layer;

depositing a control-gate polysilicon layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate polysilicon layer;

etching trenches to define a floating-gate stack; and

depositing a nitride spacer layer on sides of the trenches to isolate all sides of the floating gate polysilicon layer.

35. The method according to claim 30, further comprising:

connecting the floating-gate stack as an electrically-erasable memory; and

operably connecting the electrically-erasable memory to a microprocessor.

36. The method according to claim 30, further comprising:

connecting the floating-gate stack as an electrically-erasable memory; and

operably connecting the electrically-erasable memory to a microprocessor.

37. A method of fabricating an electronic circuit comprising:

forming a first dielectric layer on a first chip area to be used for a first set of transistors and on a second chip area to be used for a second set of transistors and on a third chip area to be used for a third set of transistors;

substantially removing the first dielectric layer from the second chip area while substantially leaving the first dielectric layer on the first chip area; and

forming a second dielectric layer on the second chip area, while thickening the dielectric of the first chip area, wherein the first dielectric layer is thicker than the second dielectric layer, wherein the first dielectric is a gate oxide for signal transistors, and the second dielectric is a gate oxide for electrically erasable and programmable read only memory (EEPROM) storage transistors that are formed by;

depositing a floating-gate poly layer over the second dielectric layer;

depositing an inter-poly nitride layer over the floating-gate poly layer;

depositing a control-gate poly layer over the inter-poly nitride layer;

depositing a tungsten-silicide (WSix) layer over the control-gate poly layer;

etching trenches to define a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, the stack including the second dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer;

etching the stack to form a drain end and a source end;

depositing a nitride layer covering the first and second side from the inter-poly nitride layer to their respective trenches, and covering the drain end and source ends from the inter-poly nitride layer to the substrate;

forming a tungsten drain contact substantially adjacent to the nitride layer covering the drain end;

forming a tungsten source contact substantially adjacent to the nitride layer covering the source end; and

forming a tungsten gate contact to substantially contact the WSix layer.

38. A method for fabricating an electronic circuit on a wafer comprising:

depositing a dielectric layer on a substrate of the wafer;

depositing a first poly gate layer over the dielectric layer;

depositing an inter-poly dielectric layer over the first poly layer;

depositing a second poly gate layer over the inter-poly dielectric layer;

removing the inter-poly dielectric and the second poly gate layer from some but not all of the first poly gate layer;

depositing a tungsten-silicide (WSix) layer over at least the second poly gate layer to reduce contact resistance; and

depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were removed, and to the second poly gate layer in an area in which the inter-poly dielectric and the second poly gate layers were not removed.

39. A method for fabricating an electronic circuit on a wafer comprising:

depositing a dielectric layer on a substrate of the wafer;

depositing a first poly gate layer over the dielectric layer;

depositing an inter-poly dielectric layer over the first poly layer;

removing the inter-poly dielectric from a first chip area but not from a second chip area; and

depositing a second poly gate layer over the inter-poly dielectric layer in the second chip area, and on the first poly gate layer in the first chip area, wherein the second poly gate layer forms a control gate for a memory cell in the second chip area.

40. The method according claim 39, further comprising:

depositing a tungsten-silicide (WSix) layer over the second poly gate layer to reduce contact resistance.

41. The method according claim 39, further comprising:

depositing a gate-signal-connection layer that forms electrical contacts to the first poly gate layer in the first chip area, and to the second poly gate layer in the second chip area.