Method of utilizing fabrication process of floating gate spacer to build twin-bit monos/sonos memory

• US 6,551,880 B1
• Filed: 05/17/2002
• Issued: 04/22/2003
• Est. Priority Date: 05/17/2002
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Liu, Chien-Hung, Huang, Shou Wei, Pan, Shyi-Shuh, Chen, Ying Tzoo
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US10/146,876
• Time in Patent Office: 340 Days
• Field of Search: 438/216, 438/261, 438/262, 438/263, 438/282, 438/287, 438/526, 438/591, 438/595, 438/954, 438/957, 438/FOR.431
• US Class Current: 438/261
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention discloses a method of utilizing the fabrication process of floating gate spacer to build a twin-bit MONOS/SONOS memory, wherein recessed ONO spacers are used to fabricate a discontinuous floating gate below a poly control gate to obtain a MONOS/SONOS memory device having twinbit memory cells. Cross talk between charges stored in the two bits can be avoided, hence enhancing the reliability of memory device. Moreover, if the voltage V_t varies during the fabrication process, the device can restore its normal characteristics through the individual and separate characteristic of the two bits and by using program or erase condition. The present invention can utilize the fabrication process of ONO spacer to complete the fabrication process of floating gate in automatic alignment way without the need of undergoing several mask processes.

Claims

1. A method of utilizing the fabrication process of floating gate spacer to build a twin-bit MONOS/SONOS memory, comprising the steps of:

forming a pad oxide and an already defined and patterned masking layer on a semiconductor substrate;

performing buried diffusion implant to said substrate to form an implanted region with said masking layer as a mask;

depositing an oxide on said substrate then planarizing said oxide to remove part of said oxide until said masking layer is exposed;

removing said masking layer, using said oxide to define the region of device, and then removing said pad oxide;

depositing an ONO film formed of a first oxide, a nitride, and a second oxide on the surface of said substrate to cover said oxide;

performing anisotropic etch to said ONO film to form ONO spacers at two sides of said oxide; and

forming an already defined polysilicon on said substrate.

2. The method as claimed in claim 1, wherein said pad oxide is a silicon oxide.

3. The method as claimed in claim 1, wherein said masking layer is a silicon nitride.

4. The method as claimed in claim 1, wherein said masking layer is formed of a patterned photo resist.

5. The method as claimed in claim 1, wherein said implanted region is an N-type implanted region.

6. The method as claimed in claim 1, wherein said oxide is a silicon oxide.

7. The method as claimed in claim 1, wherein said first oxide and said second oxide are composed of silicon oxide.

8. The method as claimed in claim 1, wherein said nitride is composed of silicon nitride.

9. The method as claimed in claim 1, wherein a gate oxide can further be deposited on said substrate before forming said polysilicon.

10. The method as claimed in claim 9, wherein said gate oxide is composed of silicon oxide.