Method of forming a spacer

• US 6,551,887 B2
• Filed: 07/16/2002
• Issued: 04/22/2003
• Est. Priority Date: 08/31/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Hyung-Shin, Joo, Joon-Yong
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US10/198,266
• Publication Number:
  US 20030045061A1
• Time in Patent Office: 280 Days
• Field of Search: 438/303, 438/305, 438/307, 438/529, 438/595
• US Class Current: 438/305
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present invention provides a method of forming a semiconductor device spacer. In the method, a gate pattern is formed on a semiconductor substrate, and a first insulation layer, a second insulation layer, and a third insulation layer are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed of the same material under a first pressure and a second pressure higher than the first pressure, respectively, and preferably of silicon nitride, using a low pressure chemical vapor deposition (LPCVD) technique. The third and second insulation layers are sequentially, anisotropically etched until the first insulation layer is exposed, thereby forming a spacer and a second insulation pattern. The spacer is selectively removed by an isotropic etching method, to minimize the recessed extent of the second insulation pattern. The exposed first insulation layer is etched to form a first insulation pattern.

Claims

1. A method of forming a spacer in a semiconductor device, comprising:

forming a gate pattern on a semiconductor substrate;

forming a first insulation layer over substantially an entire surface of the semiconductor substrate where the gate pattern is formed;

forming a second insulation layer on the first insulation layer under a first pressure;

forming a third insulation layer on the second insulation layer under a second pressure higher than the first pressure;

sequentially anisotropically etching the third and second insulation layers to form a spacer and a second insulation pattern, and to expose the first insulation layer;

removing the spacer by using an etch recipe having an etch selectivity with respect to the second insulation pattern, to expose the second insulation pattern; and

etching the first insulation layer until the semiconductor substrate is exposed, to form a first insulation pattern.

2. The method as claimed in claim 1, wherein the first insulation layer is formed of a silicon oxide layer.

3. The method as claimed in claim 1, wherein the second insulation layer and the third insulation layer are formed of the same material.

4. The method as claimed in claim 1, wherein the second insulation layer and the third insulation layer are formed of a silicon nitride layer.

5. The method as claimed in claim 1, wherein the second insulation layer and the third insulation layer are formed by using a low pressure chemical vapor deposition (LPCVD) technique.

6. The method as claimed in claim 1, wherein the second insulation layer and the third insulation layer are formed at a temperature of between approximately 500 and 700°

C.

7. The method as claimed in claim 1, wherein the first pressure is between proximately 0.01 and 1 Torr.

8. The method as claimed in claim 1, wherein the second pressure is between approximately 3 and 100 Torr.

9. The method as claimed in claim 1, wherein the first, second and third insulation layers are formed into conformal thicknesses.

10. The method as claimed in claim 1, after forming the gate pattern, further comprising:

oxidizing the exposed surface of the gate pattern and the semiconductor substrate.

11. The method as claimed in claim 10, after the gate oxidation process, further comprising:

forming a low concentration impurity region at the semiconductor substrate by performing a low concentration ion-implantation process using the gate pattern as an ion-implantation mask.

12. The method as claimed in claim 1, wherein the anisotropical etching of the third insulation layer and the second insulation layer is performed by using an etch recipe having an etch selectivity with respect to the first insulation layer.

13. The method as claimed in claim 1, wherein the removing of the spacer is performed by an isotropic etching method.

14. The method as claimed in claim 1, wherein the removing of the spacer is performed by an etch recipe having an etch selectivity with respect to the first insulation layer.

15. The method as claimed in claim 1, wherein the removing of the spacer uses an etchant including a phosphoric acid.

16. The method as claimed in claim 1, after removing the spacer, further comprising:

forming source/drain regions at the semiconductor substrate by performing a high concentration impurity-implantation process by using the second insulation pattern, the first insulation pattern and the gate pattern as ion-implantation masks.

17. The method as claimed in claim 1, before forming the gate pattern, further comprising:

forming an isolation pattern to define an active region at a predetermined region of the semiconductor substrate.