Trench gate oxide formation method

• US 6,551,900 B1
• Filed: 04/12/2000
• Issued: 04/22/2003
• Est. Priority Date: 12/09/1999
• Status: Expired due to Term

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chang, Leon, Lin, Ping-Wei, Chung, Yifu
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Keshavan, Belur V
• Application Number:
  US09/547,730
• Time in Patent Office: 1,105 Days
• Field of Search: 438/197, 438/424, 438/270, 438/248, 438/386, 438/243, 438/696, 438/699, 257/301, 257/622
• US Class Current: 438/424
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for improving gate oxide thinning issue at trench corners is disclosed. The method comprises steps as follows. Firstly, a silicon substrate having a trench therein is provided. HDPCVD technology to form a first oxide layer on the sidewall and the bottom of the trench is carried out. After performing an etchback to leave the first oxide layer on the bottom of the trench, a second oxide layer is formed on the first oxide layer and on sidewalls of the trench by LPCVD technology. Thereafter, an isotropic etching is performed so as to remove a substantially portion of the second oxide layer and leave a remnant portion of second oxide layer on the trench corners. As a consequently, the trench corners are smooth. Finally, a thermal oxidation to form a third oxide layer on the sidewall of the trench is carried achieved to accomplish the gate oxide formation.

Claims

1. A method for improving thinner gate oxide at trench corners, said method comprising the steps of:

providing a silicon substrate having a trench therein;

forming a first oxide layer on the sidewalls and bottom of said trench;

performing an etchback process to leave said first oxide layer on the bottom of said trench;

performing a LPCVD process to form a second oxide layer on said first oxide layer and the sidewalls of said trench;

performing an anneal process to make uniform said second oxide layer;

performing an isotropic etching to remove a substantially portion of said second oxide layer and to leave a remnant portion of said second oxide layer on said trench corners; and

performing a thermal oxidation process to form a third oxide layer on the sidewalls of said trench.

2. The method of claim 1, wherein said first oxide layer is formed by a HDPCVD process to a thickness of about 360-440 nm at a temperature of about 390-410°

C.

3. The method of claim 1, wherein the thickness of said first oxide layer is about 160-240 nm in thickness after said etchback process.

4. The method of claim 1, wherein said second oxide is formed at a temperature of about 700-740°

C. to about 135-165 nm.

5. The method of claim 1, wherein said step of performing annealing process is done at a temperature of about 850-950°

C.

6. The method of claim 1, wherein said isotropic etching is performed by 0.5% to 1% HF as etchant so that only a thickness about 50-100 nm of said second oxide layer is left on said trench corners.

7. The method of claim 1, wherein said third oxide layer is formed at a temperature of about 840-860°

C. to a thickness of about 45-55 nm.

8. A method for improving thinner gate oxide at trench corners, said method comprising the steps of:

providing a silicon substrate having a trench therein;

performing a LPCVD process to form a first oxide layer on sidewalls and a bottom of said trench;

performing an etchback process to leave said first oxide layer on the bottom of said trench;

forming a second oxide layer on said first oxide layer and the sidewalls of said trench by a LPCVD process,

performing an anneal process to uniform said second oxide layer;

performing an isotropic etching to remove a substantial portion of said second oxide layer and to leave a remnant portion of said second oxide layer on said trench corners; and

performing a thermal oxidation process to form a third oxide layer on the sidewall of said trench.

9. The method of claim 8, wherein said first oxide layer is formed at a temperature of about 390-410°

C. to a thickness of about 160-240 nm.

10. The method of claim 8, wherein said second oxide layer is formed at a temperature of about 700-740°

C. to about 135-165 nm in thickness.

11. The method of claim 8, wherein said third oxide layer is formed at a temperature of about 840-860°

C. to a thickness of about 45-55 nm.

12. The method of claim 8, wherein said isotropic etching is performed by 0.5% to 1% HF as etchant so that only a thickness about 50-100 nm of said second oxide layer is left on said trench corners.