Method for preventing borderless contact to well leakage

• US 6,551,901 B1
• Filed: 11/30/2001
• Issued: 04/22/2003
• Est. Priority Date: 08/21/2001
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Gu, Shiqun, McGrath, Peter, Allman, Derryl J.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/006,540
• Time in Patent Office: 508 Days
• Field of Search: 438/296, 438/424, 438/618, 438/675, 438/740, 438/763, 257/397, 257/513, 257/774
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.

Claims

1. A method of forming a semiconductor chip, comprising:

creating shallow trenches containing field oxide on a substrate;

forming at least one semiconductor device between the shallow trenches;

forming an oxide layer over the at least one semiconductor device and the field oxide, wherein the forming the oxide layer over the semiconductor device comprises;

forming a conformal oxide layer; and

etching back the conformal oxide layer;

forming an etch stop layer over the oxide layer;

forming an inter layer dielectric layer over the etch stop layer;

etching at least one contact hole through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer; and

filling the at least one contact hole with a conductive material.

2. The method, as recited in claim 1, wherein the etching back the conformal oxide layer comprises etching with an anisotropic etch to make the conformal oxide layer thinner.