Post metalization chem-mech polishing dielectric etch

• US 6,551,924 B1
• Filed: 11/02/1999
• Issued: 04/22/2003
• Est. Priority Date: 11/02/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dalton, Timothy J., Hummel, John P.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TOLEDO, FERNANDO L
• Application Number:
  US09/432,683
• Time in Patent Office: 1,267 Days
• Field of Search: 438/692, 438/700, 438/706, 438/740, 438/638, 438/637, 438/687, 438/396, 438/574, 438/619, 438/629, 438/648, 438/411, 438/421, 438/422, 438/598, 438/667, 438/669, 438/695
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielectric. A passivating layer is deposited on top of the conducting layer after the conducting layer has been planarized through chemical-mechanical polishing while simultaneously etching the dielectric layer through a process that does not damage the underlying conducting and liner layers. The insulating layer is preferably a dielectric such as silicon dioxide and the liner layer is tantalum, tantalum nitride or a combination of the two. The passivating layer preferably consists of carbon and fluorine bound up in various chemical forms. The conducting layer preferably consists of copper. Recipes for simultaneously forming the passivating layer and etching the dielectric layer, and for removing the passivating layer without damaging the underlying conducting and liner layers are provided.

Claims

1. A method for etching a dielectric layer in a semiconductor integrated circuit fabrication process without damaging an underlying layer of metalization, comprising the steps of:

patterning a dielectric layer deposited on top of a substrate;

depositing a conducting layer of metalization within the patterned dielectric layer;

planarizing the layer of metalization via a chemical mechanical polishing process; and

depositing a passivating layer on top of the layer of metalization after the metalization has been planarized and simultaneously etching the dielectric layer without damaging the conducting layer of metalization.

2. The method defined in claim 1, further comprising the step of depositing an etch stop layer prior to depositing the dielectric layer.

3. The method defined in claim 2, wherein the step of etching the dielectric layer proceeds to a stop point defined by the etch stop layer.

4. The method defined in claim 1, wherein the step of etching the dielectric layer proceeds to a level of the underlying layer of metalization.

5. The method defined in claim 1, wherein the step of etching the dielectric layer proceeds to a level below the underlying layer of metalization.

6. The method defined in claim 1, further comprising the step of patterning the dielectric layer through the use of a photoresist pattern.

7. The method defined in claim 1, wherein the step of etching the dielectric layer comprises the step of plasma etching.

8. The method defined in claim 7, wherein the plasma etch consists of a mixture of feed gases.

9. The method defined in claim 8, wherein the mixture of feed gases comprises Ar, C₂F₆, and cyclo-C₄F₈.

10. The method defined in claim 1, further comprising the step of forming a self-aligned side wall spacer formed from the dielectric layer.

11. The method defined in claim 1, wherein the etched dielectric is replaced by another dielectric layer having different properties.

12. The method defined in claim 11, wherein the different properties comprise having a lower dielectric constant.

13. The method defined in claim 1, wherein the conductor layer of metalization is encased with carbon and fluorine bound in various chemical forms.

14. The method defined in claim 1, further comprising the step of depositing a liner layer before deposition of the conducting layer of metalization.

15. The method defined in claim 1, wherein the dielectric layer comprises silicon dioxide.

16. The method defined in claim 14, wherein the liner layer comprises tantalum.

17. The method defined in claim 14, wherein the liner layer comprises tantalum nitride.

18. The method defined in claim 14, wherein the liner layer comprises tantalum and tantalum nitride.

19. The method defined in claim 1, wherein the metalization layer comprises copper.

20. The method defined in claim 1, further comprising the step of removing the passivating layer without damaging the metalization and liner layers.

21. A method for etching a dielectric layer in a semiconductor integrated circuit fabrication process without damaging an underlying layer of metalization, comprising the steps of:

depositing a first dielectric on top of a semiconductor substrate, the first dielectric having a low dielectric constant;

depositing a second dielectric on top of the first dielectric, the second dielectric having a dielectric constant higher than the first dielectric;

patterning the first and second dielectrics;

depositing a conducting layer of metalization within the patterned first and second dielectrics;

planarizing the layer of metalization via a chemical mechanical polishing process; and

depositing a passivating layer on top of the layer of metalization after the metalization has been planarized and simultaneously etching the second dielectric without damaging the conducting layer of metalization.

22. The method defined in claim 21, further comprising the step of depositing an etch stop layer prior to depositing the first dielectric.

23. The method defined in claim 21, wherein the etched second dielectric is replaced by a third dielectric having a lower dielectric constant.

24. The method defined in claim 21, further comprising the step of depositing a liner layer before deposition of the conducting layer of metalization.

25. The method defined in claim 24, wherein the liner layer comprises tantalum.

26. The method defined in claim 24, wherein the liner layer comprises tantalum nitride.

27. The method defined in claim 24, wherein the liner layer comprises tantalum and tantalum nitride.

28. The method defined in claim 21, wherein the metalization layer comprises copper.

29. The method defined in claim 21, further comprising the step of removing the passivating layer without damaging the metalization and liner layer.