Process for manufacturing a semiconductor material wafer comprising single-Crystal regions separated by insulating material regions

• US 6,551,944 B1
• Filed: 04/06/2000
• Issued: 04/22/2003
• Est. Priority Date: 04/07/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Rapisarda, Cirino, Fallica, Piero Giorgio, Patti, Davide Giuseppe
• Primary Examiner(s): Powell, William A.
• Application Number:
  US09/544,717
• Time in Patent Office: 1,111 Days
• Field of Search: 148/33, 148/33.2, 148/33.3, 257/506, 257/510, 216/2, 216/39, 216/79, 216/99, 438/359, 438/424, 438/427, 438/444, 438/719, 438/734, 438/745, 438/753
• US Class Current: 438/719
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence

Abstract

A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a width larger than the trenches; covering the walls of the cavities with dielectric material; depositing non-conducting material different from thermal oxide to fill the cavities at least partially, so as to form a single-crystal island separated from the rest of the semiconductor material body. The isotropic etching permits the formation of at least two adjacent cavities separated by a support region of semiconductor material, which is oxidized together with the walls of the cavities to provide a support to the island prior to filling with non-conducting material.

Claims

1. A process for manufacturing a wafer of semiconductor material, comprising:

carrying out a directional etching in a semiconductor material body to form trenches having a first width;

carrying out an isotropic etching of said trenches of said semiconductor material body under said trenches to form cavities having a second width larger than the first width;

covering said walls of said cavities with dielectric material;

depositing insulating material to at least partially fill said cavities so as to form a single-crystal island separated from said semiconductor material body.

2. The process of claim 1 wherein carrying out a directional etching comprises carrying out a plasma etching.

3. The process of claim 1 wherein carrying out an isotropic etching comprises carrying out a plasma etching or an acid solution etching.

4. The process of claim 1 wherein forming cavities comprises forming at least two adjacent cavities separated by a support region of semiconductor material, and wherein covering said walls comprises oxidizing said walls and said support region.

5. The process of claim 4 wherein said trenches are connected in couples and form a closed line.

6. The process of claim 1, comprising, prior to said directional etching, forming support regions of insulating material, extending transversely and adjacent to ends of said trenches.

7. The process of claim 6 wherein said support regions comprise thick oxide regions.

8. The process of claim 6 wherein said support structures comprise trenches filled with dielectric material.

9. The process of claim 4, further comprising, prior to said directional etching, carrying out a damage implant to form at least two damaged regions in adjacent and non-adjacent position and growing an epitaxial layer, and wherein carrying out an isotropic etching comprises removing said damaged regions.

10. The process of claim 9 wherein carrying out a damage implant comprises implanting a doping agent.

11. The process of claim 10 wherein said doping agent is selected from among boron, phosphorus, antimony and arsenic.

12. The process of claim 9 wherein carrying out a damage implant comprises implanting an inert material and generating crystallographic damage.

13. The process of claim 12 wherein said inert material is selected from among silicon, argon and nitrogen.

14. The process of claim 9 wherein carrying out a damage implant comprises implanting a gaseous material forming bubbles.

15. The process of claim 14 wherein said gaseous material is selected from among hydrogen and helium.

16. The process of claim 13, further comprising, after carrying out a directional etching, oxidizing said damaged regions, and further wherein carrying out an isotropic etching comprises etching said semiconductor material body and said damaged regions with hydrofluoric acid.

17. The process of claim 1 wherein said insulating material is selected from the group comprising:

undoped multi-crystal silicon, undoped amorphous silicon, and deposited silicon oxide.

18. A wafer of semiconductor material, comprising a semiconductor material body surrounding an insulating structure of non-conducting material, an island surrounded by said insulating structure and a support structure for said island, arranged laterally to or under said island, between said island and said semiconductor material body.

19. The wafer of claim 18 wherein said support structure is formed by at least one vertical support column of silicon oxide extending between said semiconductor material body and said island through the insulating structure.

20. The wafer of claim 18 wherein said support structure comprises at least one end support region of dielectric material extending between said body of semiconductor material and said island transversely and adjacent to said island.

21. The wafer of claim 20 wherein said end support region comprises a thick field oxide.

22. The wafer of claim 20 wherein said end support region is formed from a trench filled with dielectric material.

23. An integrated power device, comprising a semiconductor material body surrounding an insulating structure of non-conducting material, and an island surrounded by said insulating structure;

said semiconductor material body housing a vertical-current-flow power transistor including a buried conduction region and said island housing a low-voltage device, said buried conduction region arranged under said island and said insulating structure.

24. The device of claim 23, comprising a vertical support column of silicon oxide extending inside said insulating structure between a lower portion of said semiconductor material body and said island.

25. A process for manufacturing integrated circuits, comprising:

forming in a semiconductor material body a single-crystal island separated from the semiconductor material body with non-conductive material other than thermal oxide.

26. The process of claim 25 wherein forming the single-crystal island comprises etching one or more cavities in the semiconductor material body to isolate the single-crystal island.

27. The process of claim 26 wherein forming the one or more cavities comprises:

directionally etching the semiconductor material body to form one or more trenches; and

isotropically etching through the trenches the semiconductor material body to form cavities under the trenches, the cavities having a width greater than the width of the trenches.

28. The process of claim 27, further comprising covering the walls of the one or more cavities with a dielectric material.

29. The process of claim 27 wherein forming one or more cavities comprises forming at least two adjacent cavities separated by a wall that supports the single-crystal island in the semiconductor material body.

30. The process of claim 25 wherein forming the single-crystal island further comprises forming at least one end support region of dielectric material extending between the semiconductor material body and the single-crystal island transversely and adjacent to the single crystal island.