Hetero-junction field effect transistor having an intermediate layer

• US 6,552,373 B2
• Filed: 03/28/2001
• Issued: 04/22/2003
• Est. Priority Date: 03/28/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Ohno, Yasuo, Matsunaga, Koji, Takahashi, Yuji, Miyamoto, Hironobu, Kasahara, Kensuke, Nakayama, Tatsuo, Ando, Yuji, Hayama, Nobuyuki, Kunihiro, Kazuaki, Kuzuhara, Masaaki, Iwata, Naotaka
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US09/818,587
• Publication Number:
  US 20010040247A1
• Time in Patent Office: 755 Days
• Field of Search: 257/192-196, 257/185, 257/184, 257/187, 257/190, 257/201, 257/183, 257/12, 257/15, 257/20, 257/85, 257/94
• US Class Current: 257/192
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

Claims

1. A hetero-junction filed effect transistor (HJFET) comprising a substrate, a layer structure including an In_xGa₁₋

xN (0≦

x≦

1) channel layer, an Al_yGa<sub>1−

y</sub>N (0<

y≦

1) electron supply layer, at least one intermediate layer and an n-type GaN cap layer consecutively formed on said substrate, a gate electrode disposed in contact with said electron supply layer, and source and drain electrodes disposed in contact with said n-type cal layer, said at least one intermediate layer being formed as a single n-type-impurity doped layer or a plurality of stacked layers including at least one n-type-impurity doped layer,

wherein said n-type-impurity doped layer includes n-type impurities in a surface density (Ns cm<sup>−

2</sup>) expressed by;

2. The HJFET as defined in claim 1, wherein said n-type-impurity doped layer is an n-type Al_zGa₁₋

zN (z=y) layer.

3. The HJFET as defined in claim 1, wherein said plurality of stacked layers include a first n-type-impurity doped layer, an Al_zGa₁₋

zN (0<

z<

y) layer and a second n-type-impurity doped layer consecutively formed on said electron supply layer.

4. The HJFET as defined in claim 3, wherein said Al_zGa₁₋

zN layer has a graded composition, given z gradually decreasing from y toward zero as viewed from said electron supply layer toward said n-type cap layer.

5. The HJFET as defined in claim 3, wherein said Al_zGa₁₋

zN layer has a graded composition, given z stepwise decreasing from y toward zero as viewed from said electron supply layer toward said n-type cap layer.

6. The HJFET as defined in claim 1, wherein said n-type-impurity doped layer is an n-type Al_zGa₁₋

zN (0<

z<

y) layer.

7. The HJFET as defined in claim 6, wherein said Al_zGa₁₋

zN layer has a graded composition, given z gradually decreasing from y toward zero as viewed from said electron supply layer toward said n-type cap layer.

8. The HJFET as defined in claim 6, wherein said Al_zGa₁₋

zN layer has a graded composition, given z stepwise decreasing from y toward zero as viewed from said electron supply layer toward said n-type cap layer.

9. The HJFET as claimed in claim 1, wherein said at least one intermediate layer has a super-lattice structure including a plurality of Al_z1Ga₁₋

z1N (0<

z1≦

1) layers and a plurality of GaN layers alternately stacked, each of said Al_z1Ga<sub>1−

z1</sub>N layers and each of said GaN layers having a thickness of t1 and t2, respectively, z1×

t1/(t1+t2) monotonically decreasing from y toward zero as viewed from said electron supply layer toward said n-type cap layer.

10. The HJFET as defined in claim 1, wherein said at least one intermediate layer has a super-lattice structure including a plurality Al_z1Ga₁₋

z1N (0<

z1≦

1) layers and a plurality of GaN layers alternately stacked, each of said Al_z1Ga<sub>1−

z1</sub>N layers and each of said GaN layers having a thicknesses of t1 and t2, respectively, z1 being constant and t1/(t1+t2) monotonically decreasing from y/z1 toward zero as viewed from said electron supply layer toward said n-type cap layer.

11. The HJFET as defined in claim 1, wherein said at least one intermediate layer has a super-lattice structure including a plurality Al_z1Ga₁₋

z1N (0<

z1≦

1) layers and a plurality of GaN layers alternately stacked, each of said Al_z1Ga<sub>1−

z1</sub>N layers and each of said GaN layers having a thicknesses of t1 and t2, respectively, t1/(t1+t2) assuming a constant Γ and

z1 monotonically decreasing from y/Γ

toward zero as viewed from said electron supply layer toward said n-type cap layer.

12. A hetero-junction filed effect transistor (HJFET) comprising a substrate, a layer structure including an In_xGa₁₋

xN (0≦

x ≦

1) channel layer, an Al_yGa<sub>1−

y</sub>N (0<

y<

1) electron supply layer, at least one intermediate layer and an n-type In_uGa<sub>1−

u</sub>N cap layer consecutively formed on said substrate, a gate electrode disposed in contact with said electron supply layer, and source and drain electrodes disposed in contact with said n-type cap layer, said at least one intermediate layer being formed as a single n-type-impurity doped layer or a plurality of stacked layers including at least one n-type-impurity doped layer,

wherein said n-type-impurity doped layer includes n-type impurities in a surface density (Ns) expressed by

13. The HJFET as defined in claim 12, wherein said plurality of stacked layers include a first n-type-impurity doped layer, an In_z2Al_z1Ga₁₋

z1-z2N (0≦

z1+z2≦

1) layer and a second n-type-impurity doped layer consecutively formed on said electron supply layer.

14. The HJFET as defined in claim 13, wherein said In_z2Al_z1Ga₁₋

z1-z22N(0≦

z1+z2≦

1) layer has a graded composition, z1−

z2 monotonically decreasing from y toward −

u as viewed from said electron supply layer toward said n-type cap layer.

15. The HJFET as defined in claim 14, wherein z1 decreases from y toward zero and z2 increases from zero toward u, as viewed from said electron supply layer toward said n-type cap layer.

16. The HJFET as defined in claim 14, wherein said stacked layers include a plurality of Al_z1Ga₁₋

z1N (0≦

z1≦

y) layers and a plurality of In_z2Ga<sub>1−

z2</sub>N (0≦

z2≦

u) layers stacked alternately, given z1 decreasing from y toward zero as viewed from said electron supply layer toward In_z2Ga<sub>1−

z2</sub>N layer, given z2 increasing from zero toward u as viewed from said In_z2Ga<sub>1−

z2</sub>N layer toward said n-type cap layer.

17. The HJFET as defined in claim 12, wherein said n-type-impurity doped layer is an n-type In_z2Al_z1Ga₁₋

z1-z2N (0≦

z1+z2≦

1) layer.

18. The HJFET as defined in claim 17, wherein said In_z2Al_z1Ga₁₋

z1-z22N (0≦

z1+z2≦

1) layer has a graded composition, z1−

z2 monotonically decreasing from y toward −

u as viewed from said electron supply layer toward said n-type cap layer.

19. The HJFET as defined in claim 18, wherein z1 decreases from y toward zero and z2 increases from zero toward u, as viewed from said electron supply layer toward said n-type cap layer.

20. The HJFET as defined in claim 18, wherein said stacked layers include a plurality of Al_z1Ga₁₋

z1N (0≦

z1≦

y) layers and a plurality of In_z2Ga<sub>1−

z2</sub>N (0≦

z2≦

u) layers stacked alternately, given z1 decreasing from y toward zero as viewed from said electron supply layer toward In_z2Ga<sub>1−

z2</sub>N layer, given z2 increasing from zero toward u as viewed from said In_z2Ga<sub>1−

z2</sub>N layer toward said n-type cap layer.