Mask on a polymer having an opening width less than that of the opening in the polymer

• US 6,552,432 B2
• Filed: 08/30/2001
• Issued: 04/22/2003
• Est. Priority Date: 09/10/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Farrar, Paul A.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/944,984
• Publication Number:
  US 20020020920A1
• Time in Patent Office: 600 Days
• Field of Search: 257/621, 257/643, 257/690, 257/774, 257/775, 257/784, 257/751
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53242 the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-base techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Claims

1. An integrated-circuit assembly comprising:

one or more transistor contact regions;

an oxidation-resistant polymeric layer having one or more openings, with each opening exposing at least a portion of one of the transistor contact regions and having a respective width; and

a mask layer overlying the oxidation resistant polymeric layer having a mask opening overlying at least one of the openings in the polymeric layer, with the mask opening having a width less than the width of the one opening in the polymeric layer.

2. The integrated-circuit assembly of claim 1, wherein each of the one or more transistor contact regions comprises a contact.

3. The integrated-circuit assembly of claim 1, wherein the mask opening has one or more negative sloping sidewalls.

4. The integrated-circuit assembly of claim 1, wherein the width of the one opening in the polymeric layer is at least five percent greater than the width of the mask opening.

5. An integrated-circuit assembly comprising:

one or more transistor contact regions;

an oxidation-resistant polymeric layer having one or more openings, with each opening exposing at least a portion of one of the transistor contact regions and having a respective width;

a mask layer overlying the oxidation-resistant polymeric layer having a mask opening overlying at least one of the openings in the polymeric layer, with the mask opening having a width less than the width of the one opening in the polymeric layer;

a diffusion-barrier layer having at least a first diffusion-barrier portion on the mask layer and at least a second diffusion-barrier portion within the opening in the polymeric layer on at least one or more of the transistor contact regions; and

a copper-, gold-, or silver-based layer having at least a portion on the first diffusion-barrier portion and at least a portion on the second diffusion-barrier portion.

6. The integrated-circuit assembly of claim 5, wherein the mask opening has a width less than about 0.25 microns.