Method and apparatus for interim assembly electrical testing of circuit boards

• US 6,552,529 B1
• Filed: 12/17/2001
• Issued: 04/22/2003
• Est. Priority Date: 12/17/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Courtney, Mark G., Fasano, Benjamin V.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): NGUYEN, TRUNG Q
• Application Number:
  US10/022,270
• Time in Patent Office: 491 Days
• Field of Search: 324/158.1, 324/693, 324/715, 324/718, 324/719, 324/721, 438/5, 438/10, 438/12, 438/14, 438/17, 257/913, 257/711, 702/35
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 31/2808 Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards probe, multiprobe, probe manipulator or probe fixture G01R1/067

Abstract

A method and a structure for assembling a circuit board whereby high temperature attach devices can be electrically tested prior to the joining of permanent low temperature attach devices. A test interposer, with low temperature attach known good reference devices, is placed in electrical contact with the circuit board containing high temperature attach devices. The test interposer/circuit board assembly can be used to identify any defective high temperature attach devices which can be replaced prior to joining the permanent low temperature attach devices on the circuit board. This partial interim test, when only the high temperature attach devices are mounted on the circuit board, eliminates the need to remove known good low temperature attach devices from the circuit board during the high temperature attach device rework process.

Claims

1. A method for assembling a circuit board whereby high temperature attach devices can be electrically tested prior to the joining of permanent low temperature attach devices, the method comprising the steps of:

(a) joining at least one high temperature attach device onto a circuit board;

(b) placing a test interposer with a least one low temperature known good reference device mounted on said test interposer in electrical contact with said circuit board and said at least one high temperature attach device;

(c) testing said at least one high temperature attach device while said at least one high temperature attach device is in electrical contact with said at least one low temperature known good reference device to identify defective high temperature attach devices;

(d) removing said test interposer from said circuit board;

(e) performing the following steps only if a defective high temperature attach device is present;

(i) removing defective high temperature attach devices if any are present, from said circuit board;

(ii) joining additional high temperature attach devices to replace defective high temperature attach devices, if any are present;

(iii) placing said test interposer with said at least one low temperature known good reference device mounted on said test interposer in electrical contact with said circuit board;

(iv) retesting said at least one high temperature attach device while said at least one high temperature attach device is in electrical contact with said at least one low temperature known good reference device to identify defective high temperature attach devices;

(v) removing said test interposer from said circuit board; and

(vi) repeating steps (i) to (v) until no defective high temperature attach devices are present; and

(f) joining at least one permanent low temperature attach device on said circuit board to complete the circuit board assembly.

2. The method of claim 1 wherein said at least one high temperature attach device is a semiconductor chip joined to said circuit board using a high lead solder at approximately 360°

C.

3. The method of claim 1 wherein said at least one permanent low temperature attach device is a surface mount technology (SMT) device joined using a eutectic Pb/Sn solder at a approximately 220°

C.

4. A structure for electrically testing the high temperature attach devices on a circuit board prior to the joining of the permanent low temperature attach devices, comprising:

a circuit board;

at least one high temperature attach device joined on said circuit board;

a test interposer;

cutout areas in said test interposer corresponding to the size and location of said at least one high temperature attach device on said circuit board;

at least one low temperature known good reference device mounted on said test interposer and connected to at least one compliant connector for making electrical contact to said circuit board, said test interposer in electrical contact with said circuit board, and

said test interposer further comprising conductive vias and said at least one low temperature known good reference device is mounted on a surface of said test interposer which is not contiguous with said circuit board.

5. The structure of claim 4 wherein said cutout areas are formed in said test interposer using a laser.

6. The structure of claim 4 wherein said cutout areas are formed in said test interposer using diamond cutting.

7. The structure of claim 4 wherein said test interposer is a ceramic and said cutout areas are formed in said test interposer by green milling prior to firing said test interposer.

8. The structure of claim 4 wherein said test interposer is a low dielectric material.

9. The structure of claim 4 wherein said at least one compliant connector is a metal spring.

10. The structure of claim 4 wherein said at least one compliant connector is a conductive polymer structure.

11. The structure of claim 4 wherein said at least one compliant connector is a compressible fuzz button connector.

12. The structure of claim 4 wherein said at least one compliant connector is a gold plated leaf spring.

13. The structure of claim 4 wherein said test interposer contains gold plated nickel contact pads.

14. The structure of claim 4 wherein said test interposer contains copper contact pads.

15. The structure of claim 4 wherein said at least one low temperature known good reference device is mounted on a surface of said test interposer contiguous with said circuit board.

16. The structure of claim 4 wherein said circuit board is a ceramic chip carrier.

17. The structure of claim 4 wherein said circuit board is a plastic chip carrier.

18. The structure of claim 4 wherein said circuit board is a printed wire board (PWB).