Active matrix circuit

• US 6,552,758 B1
• Filed: 08/17/1999
• Issued: 04/22/2003
• Est. Priority Date: 04/16/1996
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Primary Examiner(s): Dudek, James
• Assistant Examiner(s): NGUYEN, DUNG T
• Application Number:
  US09/375,616
• Time in Patent Office: 1,344 Days
• Field of Search: 349/42, 349/43, 349/46, 349/139, 349/140, 257/59, 257/72
• US Class Current: 349/43
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

In an active matrix circuit, a series connection of a plurality of transistors as a switching element is provided for each pixel electrode. The transistors are controlled by different gate signal lines.

Claims

1. An active matrix circuit comprising:

a gate signal line provided over a substrate and comprising a lateral pattern and a branch pattern, said branch pattern branching out from said lateral pattern;

a first semiconductor island provided over said substrate;

a second semiconductor island provided over said substrate and provided adjacent to said first semiconductor island;

wherein said branch pattern of said gate signal line overlaps with said first semiconductor island, and said lateral pattern of said gate signal line overlaps with said second semiconductor island.

2. The circuit of claim 1 wherein said circuit is provided in HDTV.

3. An active matrix circuit comprising:

a gate signal line provided over a substrate and comprising a lateral pattern and a branch pattern, said branch pattern branching out from said lateral pattern;

a first thin film transistor comprising a first semiconductor island provided over said substrate;

a second thin film transistor comprising a second semiconductor island provided over said substrate and provided adjacent to said first semiconductor island;

wherein said branch pattern of said gate signal line overlaps with a channel forming region of said first semiconductor island, and said lateral pattern of said gate signal line overlaps with a channel forming region of said second semiconductor island, so that a selection signal is supplied to said first and second thin film transistors through said gate signal line.

4. The circuit of claim 3 wherein said first and second thin film transistors have respective lightly doped drains.

5. The circuit of claim 3 wherein said first and second thin film transistors have respective offset-gate structures.

6. The circuit of claim 3 wherein said circuit is provided in HDTV.

7. An active matrix circuit comprising:

a first gate signal line provided over a substrate;

a second gate signal line provided over said substrate and adjacent to said first gate signal line; and

a semiconductor island provided over said substrate and having a channel forming region of a first thin film transistor and a channel forming region of a second thin film transistor,

wherein said first gate signal line overlaps with said semiconductor island at said channel forming region of said first thin film transistor,

wherein said second gate signal line overlaps with said semiconductor island at said channel forming region of said second thin film transistor, and

wherein said second gate signal line overlaps with a part of said semiconductor island provided between said channel forming region of said first thin film transistor and said channel forming region of said second thin film transistor, said part being doped with the same dopant as source and drain regions of at least one of said first and second thin film transistors to constitute a capacitor comprising said part and said second gate signal line and a dielectric provided therebetween.

8. The circuit of claim 7 wherein said first and second thin film transistors have respective lightly doped drains.

9. The circuit of claim 7 wherein said first and second thin film transistors have respective offset-gate structures.

10. The circuit of claim 7 wherein said circuit is provided in HDTV.

11. An active matrix circuit comprising:

pixel electrodes arranged in matrix form over a substrate;

selection signal lines provided over said substrate, each of said selection signal lines comprising a lateral pattern and a branch pattern branching out from said lateral pattern;

data signal lines arranged so as to cross said selection signal lines;

switching elements connected to the respective pixel electrodes and the corresponding data signal lines, the switching elements comprising;

a first switching element controlled by a first selection signal line and a second selection signal line adjacent to said first selection signal line, said first switching element comprising a first semiconductor island overlapping with the lateral pattern of said first selection signal line and the branch pattern of said second selection signal line; and

a second switching element provided adjacent to said first switching element and connected to the same data signal line as said first switching element, said second switching element being controlled by said second selection signal line and a third selection signal line adjacent to said second selection signal line, said second switching element comprising a second semiconductor island overlapping with the lateral pattern of said second selection signal line and the branch pattern of said third selection signal line.

12. The circuit of claim 11 wherein said circuit is provided in HDTV.

13. An electro-optical device comprising:

a gate signal line provided over a substrate and comprising a lateral pattern and a branch pattern, said branch pattern branching out from said lateral pattern;

a first semiconductor island provided over said substrate in an active matrix region;

a second semiconductor island provided over said substrate in said active matrix region and provided adjacent to said first semiconductor island;

wherein said branch pattern of said gate signal line overlaps with said first semiconductor island, and said lateral pattern of said gate signal line overlaps with said second semiconductor island.

14. The device of claim 13 wherein said device is HDTV.

15. An electro-optical device comprising:

a gate signal line provided over a substrate and comprising a lateral pattern and a branch pattern, said branch pattern branching out from said lateral pattern;

a first thin film transistor comprising a first semiconductor island provided over said substrate in an active matrix region;

a second thin film transistor comprising a second semiconductor island provided over said substrate in said active matrix region and provided adjacent to said first semiconductor island;

wherein said branch pattern of said gate signal line overlaps with a channel forming region of said first semiconductor island, and said lateral pattern of said gate signal line overlaps with a channel forming region of said second semiconductor island, so that a selection signal is supplied to said first and second thin film transistors through said gate signal line.

16. The device of claim 15 wherein said first and second thin film transistors have respective lightly doped drains.

17. The device of claim 15 wherein said first and second thin film transistors have respective offset-gate structures.

18. The device of claim 15 wherein said device is HDTV.

19. An electro-optical device comprising:

a first gate signal line provided over a substrate;

a second gate signal line provided over said substrate and adjacent to said first gate signal line; and

a semiconductor island provided over said substrate in an active matrix region and having a channel forming region of a first thin film transistor and a channel forming region of a second thin film transistor,

wherein said first gate signal line overlaps with said semiconductor island at said channel forming region of said first thin film transistor,

wherein said second gate signal line overlaps with said semiconductor island at said channel forming region of said second thin film transistor, and

wherein said second gate signal line overlaps with a part of said semiconductor island provided between said channel forming region of said first thin film transistor and said channel forming region of said second thin film transistor, said part being doped with the same dopant as source and drain regions of at least one of said first and second thin film transistors to constitute a capacitor comprising said part and said second gate signal line and a dielectric provided therebetween.

20. The device of claim 19 wherein said first and second thin film transistors have respective lightly doped drains.

21. The device of claim 19 wherein said first and second thin film transistors have respective offset-gate structures.

22. The device of claim 19 wherein said device is HDTV.

23. An electro-optical device comprising:

pixel electrodes arranged in matrix form over a substrate;

selection signal lines provided over said substrate, each of said selection signal lines comprising a lateral pattern and a branch pattern branching out from said lateral pattern;

data signal lines arranged so as to cross said selection signal lines;

switching elements connected to the respective pixel electrodes and the corresponding data signal lines, the switching elements comprising;

a first switching element controlled by a first selection signal line and a second selection signal line adjacent to said first selection signal line, said first switching element comprising a first semiconductor island overlapping with the lateral pattern of said first selection signal line and the branch pattern of said second selection signal line; and

a second switching element provided adjacent to said first switching element and connected to the same data signal line as said first switching element, said second switching element being controlled by said second selection signal line and a third selection signal line adjacent to said second selection signal line, said second switching element comprising a second semiconductor island overlapping with the lateral pattern of said second selection signal line and the branch pattern of said third selection signal line.

24. The device of claim 23 wherein said device is HDTV.

25. A projection device comprising:

a gate signal line provided over a substrate and comprising a lateral pattern and a branch pattern, said branch pattern branching out from said lateral pattern;

a first semiconductor island provided over said substrate in an active matrix region;

a second semiconductor island provided over said substrate in said active matrix region and provided adjacent to said first semiconductor island;

wherein said branch pattern of said gate signal line overlaps with said first semiconductor island, and said lateral pattern of said gate signal line overlaps with said second semiconductor island.

26. The device of claim 25 wherein said device is HDTV.

27. A projection device comprising:

a gate signal line provided over a substrate and comprising a lateral pattern and a branch pattern, said branch pattern branching out from said lateral pattern;

a first thin film transistor comprising a first semiconductor island provided over said substrate in an active matrix region;

a second thin film transistor comprising a second semiconductor island provided over said substrate in said active matrix region and provided adjacent to said first semiconductor island;

wherein said branch pattern of said gate signal line overlaps with a channel forming region of said first semiconductor island, and said lateral pattern of said gate signal line overlaps with a channel forming region of said second semiconductor island, so that a selection signal is supplied to said first and second thin film transistors through said gate signal line.

28. The device of claim 27 wherein said first and second thin film transistors have respective lightly doped drains.

29. The device of claim 27 wherein said first and second thin film transistors have respective offset-gate structures.

30. The device, of claim 27 wherein said device is HDTV.

31. A projection device comprising:

a first gate signal line provided over a substrate;

a second gate signal line provided over said substrate and adjacent to said first gate signal line; and

a semiconductor island provided over said substrate in an active matrix region and having a channel forming region of a first thin film transistor and a channel forming region of a second thin film transistor,

wherein said first gate signal line overlaps with said semiconductor island at said channel forming region of said first thin film transistor,

wherein said second gate signal line overlaps with said semiconductor island at said channel forming region of said second thin film transistor, and

wherein said second gate signal line overlaps with a part of said semiconductor island provided between said channel forming region of said first thin film transistor and said channel forming region of said second thin film transistor, said part being doped with the same dopant as source and drain regions of at least one of said first and second thin film transistors to constitute a capacitor comprising said part and said second gate signal line and a dielectric provided therebetween.

32. The device of claim 31 wherein said first and second thin film transistors have respective lightly doped drains.

33. The device of claim 31 wherein said first and second thin film transistors have respective offset-gate structures.

34. The device of claim 31 wherein said device is HDTV.

35. A projection device comprising:

pixel electrodes arranged in matrix form over a substrate;

selection signal lines provided over said substrate, each of said selection signal lines comprising a lateral pattern and a branch pattern branching out from said lateral pattern;

data signal lines arranged so as to cross said selection signal lines;

switching elements connected to the respective pixel electrodes and the corresponding data signal lines, the switching elements comprising;

a first switching element controlled by a first selection signal line and a second selection signal line adjacent to said first selection signal line, said first switching element comprising a first semiconductor island overlapping with the lateral pattern of said first selection signal line and the branch pattern of said second selection signal line; and

a second switching element provided adjacent to said first switching element and connected to the same data signal line as said first switching element, said second switching element being controlled by said second selection signal line and a third selection signal line adjacent to said second selection signal line, said second switching element comprising a second semiconductor island overlapping with the lateral pattern of said second selection signal line and the branch pattern of said third selection signal line.

36. The device of claim 35 wherein said device is HDTV.