Circuit and method for linear control of a spread spectrum transition

• US 6,553,057 B1
• Filed: 11/09/1999
• Issued: 04/22/2003
• Est. Priority Date: 11/09/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Chen, Albert, Sha, I-Teh, Chen, Kuang-Yu
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): WILLIAMS, LAWRENCE B
• Application Number:
  US09/436,155
• Time in Patent Office: 1,260 Days
• Field of Search: 327/148-157, 331/17-34, 331/1, 375/130-376
• US Class Current: 375/130
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

A spread spectrum clock generator comprising a spread spectrum modulation circuit and a control circuit. The spread spectrum modulation circuit may be configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The control circuit may be configured to synchronize the command signal to a feedback signal. The sequence of linearity ROM codes and the sequence of spread spectrum ROM codes may be generated by predetermined mathematical formulas and optimized in accordance with predetermined criteria.

Claims

1. A spread spectrum clock generator comprising:

a spread spectrum modulation circuit configured to generate a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal; and

a control circuit configured to synchronize said command signal to a feedback signal, wherein said sequence of linearity ROM codes and said sequence of spread spectrum ROM codes are generated according to one or more predetermined mathematical formulas and optimized in accordance with predetermined criteria.

2. The spread spectrum clock generator according to claim 1, wherein said spread spectrum modulation circuit modulates said clock signal.

3. The spread spectrum clock generator according to claim 2, wherein said modulation of said clock signal can be switched on and/or off in response to said command signal.

4. The spread spectrum clock generator according to claim 1, wherein said spread spectrum clock generator is implemented on a motherboard or CPU.

5. The spread spectrum clock generator according to claim 1, wherein said control circuit is further configured to generate one or more control signals in response to (i) said command signal and (ii) said feedback signal.

6. The spread spectrum clock generator according to claim 5, wherein said control circuit comprises a first latch.

7. The spread spectrum clock generator according to claim 6, wherein said control circuit further comprises a second latch.

8. The spread spectrum clock generator according to claim 3, wherein said predetermined criteria are applied to said clock signal during a transition period when modulation is switching on.

9. The spread spectrum clock generator according to claim 1, wherein said predetermined criteria includes a predetermined maximum slew rate for said clock signal.

10. The spread spectrum clock generator according to claim 7, wherein said predetermined mathematical formulas comprise:

$\mathrm{fideal}<br><br>\left(t\right)=\mathrm{foff}-\frac{\mathrm{foff}-\mathrm{fmax}}{\mathrm{Ttotal}}·<br><br>\left(t-\mathrm{ti}\right).$

wherein (i) fideal(t) comprises an ideal function, (ii) foff comprises an unmodulated frequency of said clock signal, (iii) fmax comprises a maximum frequency of said clock signal, (iv) Ttotal comprises a total time of a transition period, (v) t comprises a current time point in said transition period Ttotal, and (vi) ti comprises a time point when said spread spectrum is on.

11. The spread spectrum clock generator according to claim 10, wherein said predetermined mathematical formulas further comprise:

$\mathrm{Min}<br><br>\left\{\frac{{\int <br><br>}_i^{i+1}<br><br>{\left[\mathrm{fideal}<br><br>\left(t\right)-f<br><br>\left(t\right)\right]}^2<br><br>\text{\hspace{1em}<br><br>}<br><br><br><br>t}{\mathrm{Ttotal}}\right\}.$

wherein f(t) comprises a change in frequency of the signal clock.

12. The spread spectrum clock generator according to claim 1, wherein:

said sequence of linearity ROM codes is optimized using a computer program to simulate transient behavior of said spread spectrum clock generator.

13. A spread spectrum clock generator comprising:

means for generating a clock signal in response to (i) a sequence of linearity ROM codes, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal; and

means for synchronizing said command signal to a feedback signal, wherein said sequence of linearity ROM codes and said sequence of spread spectrum ROM codes are generated according to one or more predetermined mathematical formulas and optimized in accordance with predetermined criteria.

14. A method of producing a low slew rate linear transition in the turn-on transient response of a spread spectrum clock generator comprising the steps of:

(A) generating a sequence of linearity ROM codes according to a predetermined mathematical formula;

(B) optimizing said sequence of linearity ROM codes according to one or more predetermined criteria; and

(C) modulating a clock signal in response to (i) said sequence of linearity ROM codes and (ii) a command signal.

15. The method according to claim 14, wherein the step of generating said sequence of linearity ROM codes further comprises the sub-steps of:

(A) selecting a number of ROM codes to be used to generate a linear frequency transition; and

(B) generating said number of ROM codes according to said predetermined mathematical formulas.

16. The method according to claim 15, wherein the step (B) further comprises the sub-steps of:

(B-1) setting operating parameters;

(B-2) defining a reverse saw-tooth equation using said operating parameters;

(B-3) building a numerical model of said turn-on transient response of said spread spectrum clock generator;

(B-4) using a least square error method to optimize said sequence of linearity ROM codes.

17. The method according to claim 16, wherein said sub-steps are performed by a computer program.

18. The method according to claim 14, wherein said step (C) further comprises the sub-step of controlling a feedback divider with said sequence of linearity ROM codes and a sequence of spread spectrum ROM codes.

19. The method according to claim 14, further comprising the step of (D) synchronizing said command signal to said feedback signal.

20. The method according to claim 19, wherein the step (D) is performed using one or more latches.