Fractional-N frequency synthesizer with fractional compensation method

• US 6,553,089 B2
• Filed: 08/29/2001
• Issued: 04/22/2003
• Est. Priority Date: 03/20/2001
• Status: Expired due to Term

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: GCT Semiconductor Incorporated
• Inventors: Lee, Kang Yoon, Huh, Hyungki, Lee, Kyeongho, Park, Joonbae, Koo, Yido, Song, Eunseok, Lee, Jeongwoo
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US09/940,807
• Publication Number:
  US 20020136341A1
• Time in Patent Office: 601 Days
• Field of Search: 375/371, 375/373, 375/374, 375/375, 375/326, 375/327, 375/376, 327/146-150, 327/155-159
• US Class Current: 375/376
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A phase-locked loop (PLL) frequency synthesizer incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider, two phase detectors each using a charge pump stage pumps. A fractional accumulator stage determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes.

Claims

1. A phase locked loop, comprising:

a first phase detector that receives an input signal and a first divided signal to output a first comparison signal;

a second phase detector that receives the input signal and a second divided signal to output a second comparison signal;

a loop filter that receives the first and second comparison signals and generates an output signal responsive to the comparison signals;

a voltage-controlled oscillator that receives the output signal from the loop filter and generates a prescribed frequency signal; and

a programmable modulus divider that receives the prescribed frequency signal and generates the first and second divided signals having a prescribed phase relationship.

2. The phase-locked loop of claim 1, further comprising a plurality of parallel switches operated by a control line, wherein each of the switches couple a corresponding one of a plurality of charge pumps to a selected one of the first and second comparison signals, depending on the position of said each switch.

3. The phase-locked loop of claim 2, wherein each of the charge pumps performs one of sourcing and sinking a prescribed amount of current to the loop filter.

4. The phase-locked loop of claim 1, wherein the first phase detector comprises:

a phase detector portion with a first output port and a second output port; and

a charge pump portion having a plurality of charge pump stages.

5. The phase-locked loop of claim 4, wherein each of the charge pump stages comprises:

a first current source and a first switch coupled in series between a first prescribed voltage and a charge pump output terminal;

a second current source and a second switch coupled in series between a second prescribed voltage and the charge pump output terminal;

a first logic gate with a first input coupled to the first output port of the phase detector portion, a second input that receives a control signal and an output port coupled to the first switch; and

a second logic gate with a first input coupled to the second output port of the phase detector portion, a second input that receives the control signal and an output port coupled to the second switch.

6. The phase-locked loop of claim 5, wherein the first and second logic gates are AND gates, wherein an output of the first and second AND gates select one of the first and second switches to couple the charge pump output terminal to one of the first and second current sources.

7. The phase-locked loop of claim 1, further comprising:

a signal delay device coupled to delay one of the first comparison signal and the second comparison signal output from the first and second phase detectors, respectively.

8. The phase-locked loop of claim 1, further comprising a signal delay device coupled to one of the first and second phase detectors.

9. The phase-locked loop of claim 8, wherein the signal delay device is one of a digital delay control circuit and an analog delay control circuit.

10. The phase-locked loop of claim 1, wherein the first and second divided signals have the same frequency.

11. The phase-locked loop of claim 1, wherein the programmable modulus divider comprises:

a first logic gate;

a second logic gate that receives a control signal;

a first flip-flop coupled to receive an output signal of the first logic gate and a clock signal from the output port of the voltage-controlled oscillator;

a second flip-flop gate coupled to receive an output signal of the first flip-flop, wherein the first and second logic gates receive an output signal of the second flip-flop; and

a third flip-flop coupled to receive an output signal from the second logic gate, wherein the first, second and third flip-flops receive the prescribed frequency signal as a clock signal, wherein an output signal of the third flip-flop is received by the first logic gate, and wherein the output signals of the first and second flip-flops are the divided signals.

12. The phase-locked loop of claim 11, wherein the first and second divided signals differ in phase by a period of the clock signal.

13. The phase-locked-loop of claim 1, wherein said prescribed phase relationship corresponds to a predetermined phase difference.

14. The phase-locked-loop of claim 13, wherein said predetermined phase difference corresponds to one period of a voltage-controlled oscillator frequency.

15. A fractional-N frequency synthesizer for a mobile terminal, comprising:

a phase detector circuit that comprises,

a first phase detector having a first input port coupled to receive a reference signal, a second input port, a third input port and an output port, and

a second phase detector having a first input port coupled to receive the reference signal, a second input port, a third input port and an output port;

a loop filter having a first input port coupled to the output ports of the first and second phase detectors and an output port;

a voltage-controlled oscillator having an input port coupled to the output port of the loop filter and transmitting a prescribed frequency signal at an output port;

a programmable modulus divider having a first output port coupled to the second input port of the first phase detector to transmit a first divided signal, a second output port coupled to the second input port of the second phase detector to transmit a second divided signal, a first input port coupled to the output port of the voltage-controlled oscillator and a second input port; and

an accumulator having a first output port coupled to the second input port of the programmable modulus divider and a second output port coupled to the third input ports of the phase detectors.

16. The fractional-N frequency synthesizer of claim 15, wherein the mobile terminal is one of a cellular phone, a personal digital assistant, a digital audio player, an Internet appliance, a remote control device and a laptop computer.

17. The fractional-N frequency synthesizer of claim 15, further comprising a plurality of switches operated by a control line, wherein each of the switches couple a corresponding one of a plurality of charge pumps to the output port of a selected one of the first phase detector and the second phase detector according to a control signal from the accumulator.

18. The fractional-N frequency synthesizer of claim 15, wherein the first phase detector and the second phase detector are of the same design.

19. The fractional-N frequency synthesizer of claim 15, wherein the first phase detector comprises:

a phase detector portion with a first output port and a second output port; and

a charge pump portion having a plurality of charge pump stages.

20. The fractional-N frequency synthesizer of claim 19, wherein each of the charge pump stages comprises:

a first current source and a first switch coupled in series between a first prescribed voltage and a charge pump output terminal;

a second current source and a second switch coupled in series between a second prescribed voltage and the charge pump output terminal;

a first logic gate with a first input port coupled to the first output port of the phase detector portion, a second input that receives a control signal and an output port coupled to the first switch; and

a second logic gate with a first input coupled to the second output port of the phase detector portion, a second input that receives the control signal and an output port coupled to the second switch.

21. The fractional-N frequency synthesizer of claim 15, further comprising a signal delay device which delays an output from one of the first and second phase detectors.

22. The fractional-N frequency synthesizer of claim 15, further comprising a signal delay device coupled to one of the first and second phase detectors.

23. The fractional-N frequency synthesizer of claim 15, wherein the programmable modulus divider comprises:

a first logic gate;

a second logic gate that receives a control signal;

a first flip-flop coupled to receive an output signal of the first logic gate and a clock signal from the output port of the voltage-controlled oscillator;

a second flip-flop gate coupled to receive an output signal of the first flip-flop, wherein the first and second logic gates receive an output signal of the second flip-flop;

a third flip-flop coupled to receive an output signal from the second logic gate, wherein the first, second and third flip-flops receive the prescribed frequency signal as a clock signal, wherein an output signal of the third flip-flop is received by the first logic gate, and wherein the output signals of the first and second flip-flops are the divided signals.

24. The fractional-N frequency synthesizer of claim 15, wherein the first and second divided signals have the same frequency, and wherein the first and second divided signals differ in phase by the period of the prescribed frequency signal from the output port of the voltage-controlled oscillator.

25. A method for generating frequency signals, comprising:

(a) dividing a frequency signal output from an oscillator by a first value to produce a first divided signal;

(b) dividing a frequency signal output from an oscillator by a second value to produce a second divided signal;

(c) comparing the first divided signal to a reference signal to generate a first control signal;

(d) comparing the second divided signal to said reference signal to generate a second control signal; and

(e) adjusting the oscillator based on the first control signal and second control signal.

26. The method of claim 25, further comprising:

selecting the first value and the second value so that the first divided signal and the second divided signal have a predetermined phase difference.

27. The method of claim 26, wherein said predetermined phase difference corresponds to one period of a voltage-controlled oscillator frequency.

28. The method of claim 25, wherein the first control signal reduces a frequency of the oscillator by a predetermined amount and the second control signal increases the frequency oscillator by a predetermined amount.

29. The method of claim 28, further comprising:

passing the first control signal and the second control signal through a loop filter, wherein the first control signal and the second control signal maintain a constant loop filter output voltage.

30. The method of claim 25, further comprising:

passing the first control signal and the second control signal through a loop filter, wherein the first control signal adds current to the loop filter and the second control signal discharges current from the loop filter, such that the first control signal and the second control signal maintain a constant loop filter output voltage.

31. The method of claim 25, further comprising:

enabling a first number of charge pumps connected to a first detector which performs step (c); and

enabling a second number of charge pumps connected to a second detector which performs step (d), wherein the first number and the second number of enabled charge pumps are based on respective phase comparisons performed by the first detector and the second detector.

32. The method of claim 31, wherein the first number and the second number of enabled charge pumps are determined by a fractional accumulator state.

33. The method of claim 32, wherein the first number of charge pumps and the second number of charge pumps, when added, total a desired division factor of a frequency synthesizer.

34. The method of claim 25, further comprising:

delaying the first control signal relative to the second control signal by an amount sufficient to reduce perturbation in a voltage of a loop filter connected to the oscillator.

35. The method of claim 25, further comprising:

delaying the first divided signal and the reference signal prior to step (c); and

comparing the second divided signal and the reference signal in step (d) without delay.

36. A phase-locked-loop, comprising:

an oscillator;

a divider which divides a frequency signal output from the oscillator by a first value to produce a first divided signal and by a second value to produce a second divided signal;

a first phase detector which compares the first divided signal to a reference signal to generate a first control signal for adjusting the oscillator; and

a second phase detector which compares the second divided signal to said reference signal to generate a second control signal for adjusting the oscillator.

37. The phase-locked-loop of claim 36, wherein the first value and the second value generate a predetermined phase difference in the first divided signal and the second divided signal.

38. The phase-locked-loop of claim 37, wherein said predetermined phase difference corresponds to one period of the oscillator frequency.

39. The phase-locked-loop of claim 36, wherein the first control signal reduces a frequency of the oscillator by a predetermined amount and the second control signal increases the frequency oscillator by a predetermined amount.

40. The phase-locked-loop of claim 39, further comprising:

a loop circuit for receiving the first control signal and the second control signal,

wherein the first control signal and the second control signal have values which maintain a constant loop filter output voltage.

41. The phase-locked-loop of claim 36,

a loop circuit for receiving the first control signal and the second control signal,

wherein the first control signal adds current to the loop filter and the second control signal discharges current from the loop filter, and wherein the first control signal and the second control signal have values which maintain a constant loop filter output voltage.

42. The phase-locked-loop of claim 36, further comprising:

a plurality of charge pumps connected to the first phase detector;

a plurality of charge pumps connected to the second phase detector;

an accumulator which generates signals for enabling predetermined ones of the charge pumps connected to the first phase detector and the second phase detector, wherein a total number of the enabled charge pumps is based on respective phase comparisons performed by the first detector and the second detector.

43. The phase-locked-loop of claim 42, wherein the total number of enabled charge pumps is determined by a fractional accumulator state.

44. The phase-locked-loop of claim 42, wherein the total number of enabled charge pumps corresponds a desired division factor of a frequency synthesizer incorporating the phase-locked-loop.

45. The phase-locked-loop of claim 36, further comprising:

a delay unit which delays the first control signal relative to the second control signal by an amount sufficient to reduce perturbation in a voltage of a loop filter connected to the oscillator.

46. The phase-locked-loop of claim 36, further comprising:

a delay unit which delays the first divided signal and the reference signal before being input into the first phase detector, wherein the second phase detector compares the second divided signal and the reference signal without delay.