Upstream/downstream local oscillator methods and structures for wireless communication system transceivers

• US 6,553,209 B1
• Filed: 09/05/2000
• Issued: 04/22/2003
• Est. Priority Date: 05/16/2000
• Status: Expired due to Fees

• Current Assignee: LG Electronics, Inc. (LG Corporation), M & D Industries International Incorporated
• Original Assignee: California Amplifier Inc.
• Inventors: Kelkar, Kris, Hornsby, James J.
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US09/655,497
• Time in Patent Office: 959 Days
• Field of Search: 455/76, 455/73, 455/84, 455/265, 455/264, 455/260, 455/259, 375/362, 375/373, 375/376, 331/2, 331/18, 331/25, 331/34, 331/46, 331/47
• US Class Current: 455/76
• CPC Class Codes: H04B 1/405 with multiple discrete channels

Abstract

Local-oscillator systems for wireless communication systems are realized with oscillator networks that are phase locked to a bit timing clock. Two of the networks provide first and second phase coherent local-oscillator signals respectively to a receiver and transmitter of a transceiver. A third oscillator system forms a phase lock loop about one of the other networks and preferably includes a crystal to enhance short term stability. Because they track the bit timing clock, the first and second local-oscillator signals phase track all communication signals in the transceiver'"'"'s communication system.

Claims

1. A method of providing phase-coherent first and second local-oscillator signals for respective conversion of downstream communication signals to downstream data signals and a corresponding bit data clock and conversion of upstream data signals to upstream communication signals, said method comprising the steps of:

providing first, second and reference oscillator signals;

locking the phase of a first frequency-divided sample of said first oscillator signal to the phase of said reference oscillator signal;

locking the phase of a frequency-divided sample of said second oscillator signal to the phase of said reference oscillator signal; and

locking the phase of a second frequency-divided sample of said first oscillator signal to the phase of a frequency-divided sample of said bit timing clock;

said first and second oscillator signals thereby converted to said phase-coherent first and second local-oscillator signals.

2. The method of claim 1, further including the steps of:

sensing an absence of said bit timing clock; and

maintaining the frequency of said reference oscillator signal substantially as it was prior to said absence.

3. The method of claim 1, wherein:

said providing step includes the step of generating said first local-oscillator signal with a first voltage-controlled oscillator; and

the first locking step includes the step of coupling, to said first voltage-controlled oscillator, a control voltage whose amplitude corresponds to a phase difference between said first frequency-divided sample of said first local-oscillator signal and said reference oscillator signal.

4. The method of claim 1, wherein:

said providing step includes the step of generating said second local-oscillator signal with a second voltage-controlled oscillator; and

the second locking step includes the step of coupling, to said second voltage-controlled oscillator, a control voltage whose amplitude corresponds to a phase difference between said frequency-divided sample of said second local-oscillator signal and said reference oscillator signal.

5. The method of claim 1, wherein:

said providing step includes the step of generating said reference local-oscillator signal with a reference voltage-controlled oscillator; and

the third locking step includes the step of coupling, to said reference voltage-controlled oscillator, a control voltage whose amplitude corresponds to a phase difference between said second frequency-divided sample of said first oscillator signal and said frequency-divided sample of said bit timing clock.

6. A local-oscillator system that provides phase-coherent first and second local-oscillator signals for respective conversion of downstream communication signals to downstream data signals and a corresponding bit data clock and conversion of upstream data signals to upstream communication signals, said method comprising the steps of:

a reference oscillator network that generates a reference clock;

a first oscillator network that generates said first local-oscillator signal and phase locks a first frequency-divided sample of said first local-oscillator signal to said reference clock; and

a second oscillator network that generates said second local-oscillator signal and phase locks a frequency-divided sample of said second local-oscillator signal to said reference clock;

wherein said reference oscillator network phase locks a second frequency-divided sample of said first local-oscillator signal to a frequency-divided sample of said bit timing clock.

7. The system of claim 6, wherein said reference oscillator network includes a reference voltage-controlled oscillator that originates said reference clock;

and further including a clamp generator that applies a clamp voltage to said reference voltage-controlled oscillator in response to an absence of said bit timing clock.

8. The system of claim 7, wherein said clamp generation circuit includes:

a switch that, when activated, couples said clamp voltage to said reference voltage-controlled oscillator;

a detector that generates a detected signal in response to said bit timing clock; and

a comparator that activates said switch in the absence of said detected signal and deactivates said switch in response to said detected signal.

9. The system of claim 6, wherein said first oscillator network includes:

a first voltage-controlled oscillator that originates said first local-oscillator signal;

a frequency divider that converts said first local-oscillator signal to said first frequency-divided sample of said first local-oscillator signal;

a phase detector that generates a control voltage in response to a phase difference between said first frequency-divided sample of said first local-oscillator signal and said reference clock; and

a filter that couples said control voltage to said first voltage-controlled oscillator.

10. The system of claim 6, wherein said second oscillator network includes:

a second voltage-controlled oscillator that originates said second local-oscillator signal;

a frequency divider that converts said second local-oscillator signal to said frequency-divided sample of said second local-oscillator signal;

a phase detector that generates a control voltage in response to a phase difference between said frequency-divided sample of said second local-oscillator signal and said reference clock; and

a filter that couples said control voltage to said second voltage-controlled oscillator.

11. The system of claim 6, wherein said reference oscillator network includes:

a reference voltage-controlled oscillator that originates said reference local-oscillator signal;

a first frequency divider that converts said first local-oscillator signal to said second frequency-divided sample of said first local-oscillator signal;

a second frequency divider that converts said bit timing clock to said frequency-divided sample of said bit timing clock;

a phase detector that generates a control signal in response to a phase difference between said second frequency-divided sample of said first local-oscillator signal and said frequency-divided sample of said bit timing clock; and

a filter that couples said control signal to said reference voltage-controlled oscillator.

12. A communications transceiver that converts downstream communication signals to downstream data signals and a corresponding bit data clock and converts upstream data signals to upstream communication signals, comprising:

a receiver that has a downconverter mixer and generates downconverted communication signals in response to said downstream communication signals and to a first local-oscillator signal that is applied to said downconverter mixer;

a demodulator in said receiver that generates said downstream data signals and a corresponding bit timing clock in response to said downconverted communication signals;

a transmitter having a modulator that generates modulated signals in response to said upstream data signals and wherein said transmitter has an upconverter mixer and generates said upstream communication signals in response to said modulated signals and a second local-oscillator signal that is applied to said upconverter mixer; and

a local-oscillator system that includes;

a) a reference oscillator network that generates a reference clock;

b) a first oscillator network that generates said first local-oscillator signal and phase locks a first frequency-divided sample of said first local-oscillator signal to said reference clock; and

c) a second oscillator network that generates said second local-oscillator signal and phase locks a frequency-divided sample of said second local-oscillator signal to said reference clock;

wherein said reference oscillator network phase locks a second frequency-divided sample of said first local-oscillator signal to a frequency-divided sample of said bit timing clock;

said first and second local-oscillator signals thereby being phase coherent.

13. The transceiver of claim 12, wherein said reference oscillator network includes a reference voltage-controlled oscillator that originates said reference clock;

and further including a clamp generator that applies a clamp voltage to said reference voltage-controlled oscillator in response to an absence of said bit timing clock.

14. The transceiver of claim 12, wherein said first oscillator network includes:

a first voltage-controlled oscillator that originates said first local-oscillator signal;

a frequency divider that converts said first local-oscillator signal to said first frequency-divided sample of said first local-oscillator signal;

a phase detector that generates a control voltage in response to a phase difference between said first frequency-divided sample of said first local-oscillator signal and said reference clock; and

a filter that couples said control voltage to said first voltage-controlled oscillator.

15. The transceiver of claim 12, wherein said second oscillator network includes:

a second voltage-controlled oscillator that originates said second local-oscillator signal;

a frequency divider that converts said second local-oscillator signal to said frequency-divided sample of said second local-oscillator signal;

a phase detector that generates a control voltage in response to a phase difference between said frequency-divided sample of said second local-oscillator signal and said reference clock; and

a filter that couples said control voltage to said second voltage-controlled oscillator.

16. The transceiver of claim 12, wherein said reference oscillator network includes:

a reference voltage-controlled oscillator that originates said reference local-oscillator signal;

a first frequency divider that converts said first local-oscillator signal to said second frequency-divided sample of said first local-oscillator signal;

a second frequency divider that converts said bit timing clock to said frequency-divided sample of said bit timing clock;

a phase detector that generates a control signal in response to a phase difference between said second frequency-divided sample of said first local-oscillator signal and said frequency-divided sample of said bit timing clock; and

a filter that couples said control signal to said reference voltage-controlled oscillator.

17. The transceiver of claim 12, wherein said receiver includes:

a low-noise amplifier that amplifies said downstream communication signals; and

a bandpass filter coupled in series with said low-noise amplifier.

18. The transceiver of claim 12, wherein said transmitter includes:

a power amplifier that amplifies said upstream communication signals; and

a bandpass filter coupled between said upconverter mixer and said power amplifier.

19. The transceiver of claim 12, further including:

an antenna; and

a diplexer that couples said downstream communication signals from said antenna to said downconverter and couples said upstream communication signals from said upconverter to said antenna.

20. A communications system, comprising:

a head end that originates and transmits downstream communication signals and receives upstream communication signals;

a plurality of transceivers that receive said downstream communication signals and transmit said upstream communication signals; and

at least one communication hub that includes at least one transponder that relays said downstream and upstream communication signals between said head end and a respective set of said transceivers;

wherein each of said transceivers includes;

a receiver that has a downconverter mixer and generates downconverted communication signals in response to said downstream communication signals and to a first local-oscillator signal that is applied to said downconverter mixer;

a demodulator in said receiver that generates said downstream data signals and a corresponding bit timing clock in response to said downconverted communication signals;

a transmitter having a modulator that generates modulated signals in response to said upstream data signals and wherein said transmitter has an upconverter mixer and generates said upstream communication signals in response to said modulated signals and a second local-oscillator signal that is applied to said upconverter mixer; and

a local-oscillator system that includes;

a) a reference oscillator network that generates a reference clock;

b) a first oscillator network that generates said first local-oscillator signal and phase locks a first frequency-divided sample of said first local-oscillator signal to said reference clock; and

c) a second oscillator network that generates said second local-oscillator signal and phase locks a frequency-divided sample of said second local-oscillator signal to said reference clock; and

wherein said reference oscillator network phase locks a second frequency-divided sample of said first local-oscillator signal to a frequency-divided sample of said bit timing clock.

21. The system of claim 20, wherein said reference oscillator network includes a reference voltage-controlled oscillator that originates said reference clock;

and further including a clamp generator that applies a clamp voltage to said reference voltage-controlled oscillator in response to an absence of said bit timing clock.

22. The system of claim 20, wherein said head end includes:

termination equipment that originates said downstream communication signals and receives upstream communication signals; and

at least one transceiver that transmits said downstream communication signals and receives said upstream communication signals.