Data processing system with fully interconnected system architecture (FISA)
First Claim
1. A system for distributed placement of a switch of a multiprocessor data processing system, said system comprising:
- a plurality of processor chips having a processor and cache and each configured with a plurality of levels of metal layer;
switch means distributed among said plurality of processor chips and fully integrated within said plurality of processor chips for providing connectivity between said processor chip and external components to said processor chip, including memory, input/output (I/O) devices, and other processor chips; and
wherein said switch means is provided at a different level of metal layer than logic components of said processor and said cache within the individual processor chips.
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Accused Products
Abstract
A Fully Interconnected System Architecture (FISA) for an improved data processing system. The data processing system topology has a processor chip and external components to the processor chip, such as memory and input/output (I/O) and other processor chips. The processor chip is interconnected to the external components via a point-to-point bus topology controlled by an intra-chip integrated, distributed switch (IDS) controller. The IDS controller provides the chip with the functionality to provide a single bus to each external component and provides an overall total bandwidth greater than traditional topologies while reducing latencies between the processor and the external components. The design of the processor chip with the intra-chip IDS controller provides a pseudo “distributed switch” which may separately access distributed external components, such as memory and I/Os, etc.
16 Citations
12 Claims
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1. A system for distributed placement of a switch of a multiprocessor data processing system, said system comprising:
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a plurality of processor chips having a processor and cache and each configured with a plurality of levels of metal layer;
switch means distributed among said plurality of processor chips and fully integrated within said plurality of processor chips for providing connectivity between said processor chip and external components to said processor chip, including memory, input/output (I/O) devices, and other processor chips; and
wherein said switch means is provided at a different level of metal layer than logic components of said processor and said cache within the individual processor chips. - View Dependent Claims (2)
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3. A multiprocessor data processing system comprising:
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a plurality of processor chips each fabricated with a plurality of levels of metal layer with processor logic located at a first metal layer; and
switch means for coupling said processor chips to components external to said processor chips, wherein said switch means is distributed among and fully integrated within a different metal layer of each of said processor chips and provides direct point-to-point interconnects between said processor chips and said external components. - View Dependent Claims (4, 5, 6)
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7. A microprocessor chip comprising:
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a processor unit;
switching means for coupling said processor unit to data processing system components external to said chip, wherein said switching means is placed on and integrated with said microprocessor chip; and
wherein further said chip is a multi-layered chip and said switching means is integrated within an upper level metal layer of said chip. - View Dependent Claims (8, 9, 10, 11)
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12. A fully interconnected switching architecture for a data processing system comprising:
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a processor chip;
a component external to said processor chip;
connection means for providing point-to-point interconnection between said processor chip and said external component, wherein said connection means is controlled by an on-chip, integrated, distributed, switch controller; and
wherein further said on-chip, integrated, distributed, switch controller is designed within an upper level metal layer of said processor chip.
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Specification