Synchronous memory device having a temperature register

• US 6,553,452 B2
• Filed: 01/18/2002
• Issued: 04/22/2003
• Est. Priority Date: 10/10/1997
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Sidiropoulos, Stefanos, Stark, Donald C., Portmann, Clemenz, Davis, Paul G., Donnelly, Kevin S., Chau, Pak Shing, Garlepp, Bruno Werner
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US10/051,957
• Publication Number:
  US 20020087820A1
• Time in Patent Office: 459 Days
• Field of Search: 711/105, 711/156, 711/167, 365/212
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A synchronous dynamic random access memory device having an array of dynamic memory cells. The memory device includes input receiver circuitry to sample a value that is representative of a range of temperatures. In addition, the memory device includes a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.

Claims

1. A synchronous dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises:

input receiver circuitry to sample an externally provided value that is representative of a range of temperatures; and

a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.

2. The memory device of claim 1, further including a register to store data transfer rate information, wherein an internal circuit is adjusted based on the data transfer rate information and the value stored in the programmable register.

3. The memory device of claim 2, further including a clock synchronization circuit to receive an external clock signal and synchronize outputting of data from the memory device with the external clock signal.

4. The memory device of claim 3, wherein the clock synchronization circuit includes one of a delay locked loop circuit and a phase locked loop circuit.

5. The memory device of claim 3, wherein the clock synchronization circuit includes:

a phase detector to generate information representative of a difference in phase between the external clock signal and an internal clock signal; and

a delay circuit to generate the internal clock signal, wherein an amount of delay of the internal clock signal is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal.

6. The memory device of claim 3, wherein the programmable register is coupled to the clock synchronization circuit, and wherein the clock synchronization circuit is adjusted in accordance with the value stored within the programmable register.

7. The memory device of claim 3, wherein the clock synchronization circuit includes a mixer circuit to vary a phase of an internal clock signal in response to the value stored in the programmable register.

8. The memory device of claim 1, further including decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

9. The memory device of claim 1, further including a register to store information indicative of a length of an external signal line coupled to the memory device, wherein the memory device tunes an internal circuit based on the value stored within the programmable register and the information indicative of the length of the external signal line.

10. The memory device of claim 1, further including a register to store supply voltage information, wherein the memory device tunes an internal circuit based on the supply voltage information and the value stored within the programmable register.

11. A method of controlling a synchronous dynamic random access memory device by a memory controller, wherein the method comprises:

in the memory controller, generating information indicative of a temperature range; and

providing the information indicative of the temperature range to the memory device, wherein the memory device receives the information and stores the information in a register on the memory device.

12. The method of claim 11, wherein the information indicative of the temperature range is provided to the memory device during initialization of the memory device.

13. The method of claim 11, further including providing information indicative of a data transfer rate to the memory device, wherein the memory device times internal circuitry based on the temperature information and the information indicative of the data transfer rate.

14. The method of claim 11, wherein the memory controller is coupled to the memory device via an external signal line, the method further including:

in the controller device, detecting the length of the external signal line; and

providing a value representative of the length of the external signal line to the memory device, wherein the memory device tunes internal circuitry based on the temperature information and the value representative of the length of the external signal line.

15. The method of claim 11, further including:

detecting supply voltage information; and

providing the supply voltage information to the memory device, wherein the memory device tunes internal circuitry based on the temperature information and the supply voltage information.

16. A method of operation in a memory device that includes a plurality of memory cells, the method comprising:

receiving, from a controller, a value which is representative of a range of temperatures; and

storing the value in a programmable register on the memory device.

17. The method of claim 16, wherein the value is issued to the memory device during an initialization period.

18. The method of claim 16, further including tuning an internal circuit based on the value that is representative of a range of temperatures.

19. The method of claim 16, further including:

decoding the value to generate an internal control signal; and

adjusting an internal clock synchronization circuit in response to the internal control signal.

20. The method of claim 19, wherein adjusting the internal clock synchronization circuit includes adjusting a phase mixer in accordance with the value.

21. The method of claim 19, wherein the clock synchronization circuit is a delay lock loop circuit, wherein the delay lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal.

23. The method of claim 16, further including:

receiving a value that is representative of one of a plurality of data transfer rates; and

tuning an internal circuit based on the value that is representative of the one of the plurality of data transfer rates.

24. The method of claim 16, further including adjusting a locking frequency range of an internal clack synchronization circuit, wherein the locking frequency range is adjusted based on the value stored in the programmable register.

25. The method of claim 16, further including generating an internal clock signal having a predetermined phase relationship with an external clock signal, wherein the internal clock signal synchronizes the outputting of data from the memory device.

26. The method of claim 25, further including:

detecting a phase differential between the external clock signal and the internal clock signal;

generating the internal clock signal using a plurality of delay elements; and

varying the amount of delay in each delay element based on the phase differential.

27. The method of claim 16, further including:

receiving supply voltage information from the controller; and

storing the supply voltage information within the memory device.

28. The method of claim 16, further including:

receiving information which is representative of a data transfer rate from the controller; and

storing the information which is representative of a data transfer rate in a register disposed within the memory device.

22. The method of 19, wherein the clock synchronization circuit is a phase lock loop circuit, wherein the phase lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal.

29. An integrated circuit device having an array of memory cells, wherein the integrated circuit device comprises:

a programmable register to store a value that is representative of a range of temperatures; and

a clock synchronization circuit to receive an external clock signal and generate an internal clock signal, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register, wherein the clock synchronization circuit includes;

a phase detector to generate information representative of a difference in phase between the external clock signal and the internal clock signal; and

a delay element to generate the internal clock signal, wherein an amount of delay of the delay element is varied based on the information representative of the difference in phase between the external clock signal and the internal clock signal; and

output driver circuitry to output data in response to the internal clock signal.

30. The integrated circuit device of claim 29, wherein the clock synchronization circuit further includes a mixer circuit to vary a phase range of the internal clock signal in response to the value stored in the programmable register.

31. The integrated circuit device of claim 29 further including decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

32. The integrated circuit device of claim 29, further including a register to store information that is representative of a length of an external signal line coupled to the integrated circuit device, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register and the information that is representative of the length of the external signal line.

33. The integrated circuit device of claim 29, further including a register to store supply voltage information, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register and the supply voltage information.

34. The integrated circuit device of claim 29, further including a register to store data transfer rate information, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register and the data transfer rate information.

35. An integrated circuit device having an array of memory cells, wherein the integrated circuit device comprises:

a programmable register to store a value that is representative of the range of temperatures; and

a clock synchronization circuit to receive an external clock signal and generate an internal clock signal, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register, wherein the clock synchronization circuit includes;

a phase detector to generate information representative of a difference in phase between the external clock signal and the internal clock signal; and

an oscillator circuit, coupled to the phase detector, to generate the internal clock signal, wherein a phase of the internal clock signal is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal; and

output driver circuitry to output data in response to the internal clock signal.

36. The integrated circuit device of claim 35, wherein the clock synchronization circuit further includes a mixer circuit.

37. The integrated circuit device of claim 35, further including decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

38. The integrated circuit device of claim 35, further including a circuit to store information indicative of a length of an external signal line coupled to the integrated circuit device.

39. The integrated circuit device of claim 35, further including a circuit to store supply voltage information.

40. The integrated circuit device of claim 35, further including a circuit to store data transfer rate information.

41. A synchronous integrated circuit memory device having an array of dynamic memory cells, wherein the memory device comprises:

transceiver circuitry including;

a plurality of input receivers to receive an externally provided value that is representative of a range of temperatures; and

a plurality of output drivers to transmit data;

a locked loop circuit, coupled to the plurality of output drivers, to synchronize transmission of data from the memory device with an external clock signal; and

a programmable register, coupled to the plurality of input receivers, to store the value that is representative of a range of temperatures.

42. The memory device of claim 41, wherein the transmission of data is synchronized to the external clock signal using an internal clock signal, wherein the locked loop circuit further includes:

a phase detector to generate information representative of a phase difference between the external clock signal and the internal clock signal; and

a delay element to generate the internal clock signal, wherein an amount of delay of the delay element is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal.

43. The memory device of claim 42, wherein the clock synchronization circuit further includes a mixer circuit to vary a phase of the internal clock signal in response to the value stored in the programmable register.

44. The memory device of claim 41, wherein the transmission of data is synchronized to the external clock signal using an internal clock signal, wherein the locked loop circuit further includes:

a phase detector to generate information representative of a phase difference between the external clock signal and the internal clock signal; and

an oscillator circuit, coupled to the phase detector, to generate the internal clock signal, wherein a phase of the internal clock signal is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal.

45. The memory device of claim 44, wherein the locked loop circuit further includes a mixer circuit to vary a phase range of the internal clock signal in response to the value stored in the programmable register.