System and method for managing the execution of instruction groups having multiple executable instructions

• US 6,553,480 B1
• Filed: 11/05/1999
• Issued: 04/22/2003
• Est. Priority Date: 11/05/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Le, Hung Qui, Cheong, Hoichi
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/434,095
• Time in Patent Office: 1,264 Days
• Field of Search: 712/23, 712/244, 712/213
• US Class Current: 712/23
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A group completion table (GCT) that manages the execution of instruction groups having more than one executable instruction is disclosed. The GCT includes a plurality of table entries, wherein each of the table entries is associated with a respective instruction group. Each table entry in the GCT includes a plurality of instruction completion identifiers, wherein each of the instruction completion identifiers corresponds to a specific instruction in the associated instruction group. The table entry also includes a trouble identifier that is utilized to flag the occurrence of any exception condition encountered in the execution of any instruction in the instruction group. In a related embodiment, the trouble identifier utilized in the table entry is a single bit.

Claims

1. A group completion table (GCT) that manages execution of instruction groups having more than one executable instruction, said GCT comprising:

a plurality of table entries, wherein each of said plurality of table entries is associated with a respective instruction group and includes;

a plurality of instruction completion identifiers, each of said plurality of instruction completion identifiers corresponding to a specific instruction in said associated instruction group; and

a trouble identifier that will flag the occurrence of any exception condition in the execution of said instruction group;

wherein each of said instruction group is associated with a group tag number, and

wherein an instruction in an instruction group is identified by said instruction group'"'"'s group tag number concatenation with a multiple bit mask, wherein said mask indicating the location of said instruction in said instruction group.

2. The GCT as recited in claim 1 wherein said trouble identifier is a single bit.

3. The GCT as recited in claim 1 wherein said table entry further comprises a single exception information identifier for all instructions in said associated instruction group.

4. The GCT as recited in claim 1 wherein said GCT has twenty table entries.

6. The GCT as recited in claim 1 wherein said instruction group has five instruction.

5. A group completion table (GCT) that manages execution of instruction groups having more than one executable instruction, said GCT comprising:

a plurality of write ports, each receiving instruction groups; and

a plurality of table entries, wherein each of said plurality of table entries is associated with a respective instruction group and includes;

a plurality of instruction completion identifiers, each of said plurality of instruction completion identifiers corresponding to a specific instruction in said associated instruction group; and

a trouble identifier that will flag the occurrence of any exception condition in the execution of said instruction group.

7. A group completion table (GCT) that manages execution of instruction groups having more than one executable instruction, said GCT comprising:

a plurality of table entries, wherein each of said plurality of table entries is associated with a respective instruction group and includes;

a plurality of instruction completion identifiers, each of said plurality of instruction completion identifiers corresponding to a specific instruction in said associated instruction group;

a trouble identifier that will flag the occurrence of any exception condition in the execution of said instruction group; and

wherein a last instruction in said instruction group is a delimiter identifier.

8. The GCT as recited in claim 7 wherein said delimiter identifier is a branch (BR) instruction.

9. The GCT as recited in claim 7 wherein said delimiter identifier is a no-operation (no-op) instruction.

10. A method for managing the execution of an instruction group having more than one executable instruction, comprising the steps of:

assigning a group identifier to said instruction group;

associating a table entry in a group completion table with said instruction group using said group identifier;

indicating the completion of each executable instruction in said instruction group using a plurality of instruction completion identifiers within said table entry, each of said plurality of instruction completion identifiers corresponding to a specific instruction in said instruction group;

setting, in response to encountering at least one exception condition in the execution of said instruction group, a trouble identifier within said table entry; and

flushing an instruction group in response to said trouble identifier being set in an associated table entry of said instruction group;

wherein said step of flushing an instruction group includes the step of generating a flush mask to all execution units; and

wherein said step of flushing an instruction an instruction group includes the step of identifying said instruction group using its group identifier.

11. The method as recited in claim 10 further comprising the step of utilizing, in response to encountering exception conditions in the execution of said instruction group, a single exception information identifier within said table entry.

12. The method as recited in claim 10 wherein said trouble identifier is a single bit.

13. The method as recited in claim 10 wherein said step of flushing includes the steps of:

refetching said instruction group;

breaking said refetched instruction group into individual executable instructions; and

executing said individual instructions separately.

14. The method as recited in claim 13 wherein said step of refetching said instruction group includes the step of utilizing an effective address (EA) of a first instruction in said instruction group.

15. A method for managing the execution of an instruction group having more than one executable instruction, comprising the steps of:

assigning a group identifier to said instruction group;

associating a table entry in a group completion table with said instruction group using said group identifier;

indicating the completion of each executable instruction in said instruction group using a plurality of instruction completion identifiers within said table entry, each of said plurality of instruction completion identifiers corresponding to a specific instruction in said instruction group;

setting, in response to encountering at least one exception condition in the execution of said instruction group, a trouble identifier within said table entry;

flushing an instruction group in response to said trouble identifier being set in an associated table entry of said instruction group; and

wherein said step of flushing an instruction group includes the step of setting said instruction completion identifiers associated with the rest of said executable instructions to indicate completion in response to said setting of said trouble identifier by the next-to-complete executable instruction in said instruction group.

16. A method for managing the execution of a plurality of instruction groups, wherein each of said plurality of instruction groups having more than one executable instruction, comprising the steps of:

assigning a different group identifier to each of said plurality of instruction groups;

associating a separate table entry in a group completion table with each of said plurality of instruction groups using said group identifiers;

indicating the completion of each executable instruction in each of said plurality of instruction groups using a plurality of instruction completion identifiers within each of said table entries, each of said plurality of instruction completion identifiers corresponding to a specific instruction in each of said plurality of instruction groups;

setting, in response to encountering an exception condition in the execution of said plurality of instruction groups, a trouble identifier within said associated table entry;

flushing said plurality of instruction groups in response to said trouble identifier being set; and

flushing said plurality of instruction groups includes the step of generating a flush mask.

17. The method as recited in claim 16 wherein the number of bits in said flush mask is equal to the number of table entries in said group completion table.

18. The method as recited in claim 17 wherein said location of each bit in said flush mask corresponds to said group identifier of said plurality of instruction groups.

19. A method for managing the execution of a plurality of instruction groups, wherein each of said plurality of instruction groups having more than one executable instruction, comprising the steps of:

assigning a different group identifier to each of said plurality of instruction groups;

associating a separate table entry in a group completion table with each of said plurality of instruction groups using said group identifiers;

indicating the completion of each executable instruction in each of said plurality of instruction groups using a plurality of instruction completion identifiers within each of said table entries, each of said plurality of instruction completion identifiers corresponding to a specific instruction in each of said plurality of instruction groups;

setting, in response to encountering an exception condition in the execution of said plurality of instruction groups, a trouble identifier within said associated table entry; and

marking all younger instructions in a next-to-complete instruction group as finished in response to an older instruction in said next-to-complete instruction group encountering an exception condition.

20. A processor, comprising:

a plurality of execution units; and

a group completion table (GCT) that manages execution of instruction groups having more than one executable instruction, said GCT including;

a plurality of write ports coupled to said plurality of execution units; and

a plurality of table entries, wherein each of said plurality of table entries is associated with a respective instruction group and includes;

a plurality of instruction completion identifiers, each of said plurality of instruction completion identifiers corresponding to a specific instruction in said associated instruction group; and

a trouble identifier that will flag the occurrence of any exception condition in the execution of said instruction group;

wherein each of said instruction group is associated with a group tag number; and

wherein an instruction in an instruction group is identified by said instruction group'"'"'s group tag number concatenation with a multiple bit mask, wherein said mask indicating the location of said instruction in said instruction group.

21. The processor as recited in claim 20 wherein said trouble identifier is a single bit.

22. The processor as recited in claim 20 wherein said table entry further comprises a single exception information identifier for all instructions in said associated instruction group.

23. The processor as recited in claim 20 wherein said instruction group has five instructions.

24. The processor as recited in claim 20 wherein said GCT has twenty table entries.

25. A processor, comprising:

plurality of execution units; and

a group completion table (GCT) that manages execution of instruction groups having more than one executable instruction, said GCT including;

a plurality of write ports coupled to sad plurality of execution units; and

a plurality of table entries, wherein each of said plurality of table entries is associated with a respective instruction group and includes;

a plurality of instruction completion identifiers, each of said plurality of instruction completion identifiers corresponding to a specific instruction in said associated instruction group;

a trouble identifier that will flag the occurrence of any exception condition in the execution of said instruction group;

wherein a last instruction in said instruction group is a delimiter identifier.

26. The processor as recited in claim 25 wherein said delimiter identifier is a branch (BR) instruction.

27. The processor as recited in claim 25 wherein said delimiter identifier is a no-operation (no-op) instruction.