System and method for smart card with memory

• US 6,553,481 B1
• Filed: 04/18/2000
• Issued: 04/22/2003
• Est. Priority Date: 04/18/2000
• Status: Expired due to Fees

• Current Assignee: Swapcard.Com Inc.
• Original Assignee: Swapcard.Com Inc.
• Inventors: Langton, Philip Sydney
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/551,735
• Time in Patent Office: 1,099 Days
• Field of Search: 713/600, 710/52, 711/100, 711/101, 712/1, 712/32, 712/36, 712/37
• US Class Current: 712/37
• CPC Class Codes: G06F 9/24 Loading of the microprogram

Abstract

A system method and computer program for smart card with memory is disclosed. A very low cost approach two embodiment is disclosed, making use of a microcontroller with a FLASH memory or a WORM memory. An approach two programming a flash memory under the control of instructions within that memory itself is disclosed.

Utilizing the invention it is possible to build smart cards at a low cost them heretofore.

Claims

1. A storage device comprising:

a wireless data transmitter;

a wireless data receiver;

a clock circuit for generating a plurality of clock signals having a periodicity;

a computing engine coupled to an energy source, the wireless data transmitter,

the wireless data receiver, the clock circuit and a set of operator controls,

the computing engine comprising a volatile memory and a non-volatile memory containing a data set, the non-volatile memory further containing a set of instruction codes,

wherein the computing engine is powered by the energy source and

executes instructions selected from the set of instruction codes, and

wherein the computing engine performs an action selected from a list consisting of receiving data from the wireless data receiver and sending data to the wireless data transmitter in response to a stimulus from a control selected from the set of operator controls;

a plurality of buffers, the buffers being external to the computing engine;

a reset circuit coupled to the computing engine for initializing the computing engine; and

a programming circuit coupled to the computing engine for writing to the data set in response to a signal from the computing engine and according to the contents of the plurality of buffers

wherein the programming circuit holds the computing engine in a reset state for a duration exceeding about eight periods of the clock signals while data is being written to the data set.

2. The device of claim 1 wherein the energy source consists essentially of at least one electrochemical cell.

3. The device of claim 2 wherein the at least one electrochemical cell comprises a primary cell.

4. The device of claim 1 wherein the non-volatile memory is a FLASH memory.

5. The device of claim 1 wherein the non-volatile memory is a WORM memory.

6. The device of claim 1 wherein the non-volatile memory is an EPROM memory.

7. The device of claim 1 wherein the non-volatile memory is an PROM memory.

8. The device of claim 1 wherein the wireless data transmitter is an infrared device and wireless data receiver is a further infrared device.

9. The device of claim 1 wherein

the set of operator controls comprises a switch wherein operation of the switch energizes the microcontroller and signals the microcontroller to perform an action selected from a list consisting of sending data via the wireless transmitter and receiving data via the wireless receiver.

10. A storage device consisting essentially of:

an energy source consisting essentially of at least one electrochemical cell;

a wireless data transmitter;

a wireless data receiver;

a clock circuit for generating a plurality of clock signals having a periodicity;

a computing engine coupled to the energy source, the wireless data transmitter,

the wireless data receiver, the clock circuit and a set of operator controls,

the computing engine comprising a volatile memory and a non-volatile memory containing a data set, the non-volatile memory further containing a set of instruction codes,

wherein the computing engine is powered by the energy source and executes instructions selected from the set of instruction codes, and

wherein the computing engine performs an action selected from a list consisting of receiving data from the wireless data receiver and sending data to the wireless data transmitter in response to a stimulus from a control selected from the set of operator controls;

a plurality of buffers, the buffers being external to the computing engine;

a reset circuit coupled to the computing engine for initializing the computing engine; and

a programming circuit coupled to the computing engine for writing to the data set in response to a signal from the computing engine and according to the contents of the plurality of buffers

wherein the programming circuit holds the computing engine in a reset state for a duration exceeding about eight periods of the clock signals while data is being written to the data set.

11. The device of claim 10 wherein the non-volatile memory is a FLASH memory.

12. The device of claim 10 wherein the non-volatile memory is a WORM memory.

13. The device of claim 10 wherein the non-volatile memory is an EPROM memory.

14. The device of claim 10 wherein the non-volatile memory is an PROM memory.

15. The device of claim 10 wherein the energy source is a single electrochemical cell.

16. The device of claim 10 wherein the wireless data transmitter is an infrared device and wireless data receiver is a further infrared device.

17. A storage device consisting essentially of:

an energy source consisting essentially of at least one electrochemical cell;

a wireless data transmitter;

a wireless data receiver;

a set of operator controls comprising at least one switch;

a clock circuit for generating a plurality of clock signals having a periodicity;

a computing engine coupled to the energy source, the wireless data transmitter,

the wireless data receiver, the clock circuit and the set of operator controls,

the computing engine comprising a volatile memory and a non-volatile memory containing a data set, the non-volatile memory further containing a set of instruction codes,

wherein the computing engine is powered by the energy source and executes instructions selected from the set of instruction codes, and

wherein the computing engine performs an action selected from a list consisting of receiving data from the wireless data receiver and sending data to the wireless data transmitter in response to a stimulus from a control selected from the set of operator controls;

a plurality of buffers, the buffers being external to the computing engine;

a reset circuit coupled to the computing engine for initializing the computing engine; and

a programming circuit coupled to the computing engine for writing to the data set in response to a signal from the computing engine and according to the contents of the plurality of buffers

wherein the programming circuit holds the computing engine in a reset state for a duration exceeding about eight periods of the clock signals while data is being written to the data set.

18. The device of claim 17 wherein the operator controls comprise a first switch and a second switch, wherein operation of the first switch energizes the microcontroller and signals the microcontroller to send data via the wireless transmitter and wherein operation of the second switch energizes the microcontroller and signals the microcontroller to receive data via the wireless receiver.