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Memory device including redundancy routine for correcting random errors

  • US 6,553,510 B1
  • Filed: 09/02/1999
  • Issued: 04/22/2003
  • Est. Priority Date: 09/02/1999
  • Status: Expired due to Term
First Claim
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1. A memory device comprising:

  • an array of primary memory cells;

    redundant memory cells;

    access circuitry coupled to the array of primary memory cells and the redundant memory cells for selectively accessing either primary memory cells or redundant memory cells in response to externally provided address signals;

    a plurality of non-volatile fuse cells coupled to the access circuitry to determine if the primary memory cells or above redundant memory cells are selectively accessed in response to the externally provided address signals; and

    control circuitry to detect a primary memory cell failure encountered during either a program or an erase operation, the control circuitry is coupled to the plurality of non-volatile fuse cells to selectively program the fuse cells in response to a detected failure, wherein the control circuitry detects a primary memory cell failure by monitoring a number of consecutive program operations performed on a primary memory cell.

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