Memory device including redundancy routine for correcting random errors

• US 6,553,510 B1
• Filed: 09/02/1999
• Issued: 04/22/2003
• Est. Priority Date: 09/02/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Duncan, Marc M
• Application Number:
  US09/388,687
• Time in Patent Office: 1,328 Days
• Field of Search: 714/5, 714/6, 714/7, 714/8, 714/42, 714/710, 714/711, 714/48, 365/200
• US Class Current: 714/6.12
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A memory device and method the pact random memory cell failures in a packaged memory device. The memory device is automatically programmed to replace a defective memory cell with an available redundant memory cells. The defective memory cell can be detected during either an erase operation or a program operation. The redundant memory cells can be located in a separately erasable location from primary memory cells to allow data stored in the primary memory cells to be copied to the redundant memory cells when a defect is detected during a program operation.

Claims

1. A memory device comprising:

an array of primary memory cells;

redundant memory cells;

access circuitry coupled to the array of primary memory cells and the redundant memory cells for selectively accessing either primary memory cells or redundant memory cells in response to externally provided address signals;

a plurality of non-volatile fuse cells coupled to the access circuitry to determine if the primary memory cells or above redundant memory cells are selectively accessed in response to the externally provided address signals; and

control circuitry to detect a primary memory cell failure encountered during either a program or an erase operation, the control circuitry is coupled to the plurality of non-volatile fuse cells to selectively program the fuse cells in response to a detected failure, wherein the control circuitry detects a primary memory cell failure by monitoring a number of consecutive program operations performed on a primary memory cell.

2. The memory device of claim 1, wherein the array of primary memory cells comprise an array of flash memory cells.

3. The memory device of claim 1, wherein the redundant memory cells comprise flash memory cells.

4. The memory device of claim 1 wherein the control circuitry detects a primary memory cell failure by monitoring a number of consecutive erase operations performed on a primary memory cell.

5. The memory device of claim 1 wherein the memory device is a flash memory.

6. The memory device of claim 1 wherein the array of primary memory cells and the redundant memory cells are located in a common erasable memory block.

7. The memory device of claim 1 wherein the array of primary memory cells and the redundant memory cells are separately erasable.

8. A method of correcting random memory cell failures in a memory device, the method comprising:

initiating a program operation on a plurality of primary memory cells;

individually verifying each one of the plurality of primary memory cells to determine in each memory cell has been properly programed;

applying one or more additional program operations on a defective one of the plurality of primary memory cells which fails to properly verify that the program operation was successful; and

programming access circuitry to replace the defective memory cell with an available redundant memory cell.

9. The method of claim 8 wherein the program operation comprises applying a voltage pulse to the primary memory cell.

10. The method of claim 9 wherein the access circuitry is programmed after a predetermined number of voltage pulses has been applied to the primary memory cell.

11. The method of claim 8 wherein the plurality of primary memory cells and the available redundant memory cell are located in a separately erasable memory locations of the memory device, such that the redundant cell can be erased without erasing the primary memory cells.

12. The method of claim 8 wherein the access circuitry is programmed by selectively programming a plurality of non-volatile fuse cells.

13. The method of claim 8, wherein initiating the program operation on the plurality of primary memory cells comprises initiating the program of operation on a plurality of flash memory cells.

14. A method of correcting random memory cell failures in a memory device, the method comprising:

initiating a program operation on a primary memory cell located in a first memory array column;

detecting that the primary memory cell is defective;

programming access circuitry to replace the first memory array column comprising the defective memory cell with an available redundant memory cell column of redundant memory cells; and

copying data stored in the first memory array column to corresponding redundant memory cells located in the available redundant memory cell column, wherein detecting at the primary memory cell is defective comprises performing a plurality of consecutive program verification operations.

15. A method of correcting random memory cell failures in a memory device, the method comprising:

initiating a program operation on a plurality of primary flash memory cells;

individually verifying each one of the plurality of primary flash memory cells to determine in each memory cell has been properly programed;

applying one or more additional program operations on a defective one of the plurality of primary flash memory cells which fails to properly verify that the program operation was successful; and

programming access circuitry to replace the defective memory cell with an available redundant memory cell.

16. A method of correcting random memory cell failures in a memory device, the method comprising:

initiating a program operation on a plurality of primary dynamic random access memory (DRAM) cells;

individually verifying each one of the plurality of primary DRAM cells to determine in each memory cell has been properly programed;

applying one or more additional program operations on a defective one of the plurality of primary DRAM cells which fails to properly verify that the program operation was successful; and

programming access circuitry to replace the defective memory cell with an available redundant memory cell.

17. A method of correcting random memory cell failures in a memory device, the method comprising:

initiating a program operation on a plurality of primary static random access memory (SRAM) cells;

individually verifying each one of the plurality of primary SRAM memory cells to determine in each memory cell has been properly programed;

applying one or more additional program operations on a defective one of the plurality of primary SRAM cells which fails to properly verify that the program operation was successful; and

programming access circuitry to replace the defective memory cell with an available redundant memory cell.

18. A method of correcting random memory cell failures in a memory device, the method comprising:

initiating a program operation on a plurality of primary synchronous dynamic random access memory (SDRAM) cells;

individually verifying each one of the plurality of primary synchronous dynamic access memory (SDRAM) cells to determine in each memory cell has been properly programed;

applying one or more additional program operations on a defective one of the plurality of primary synchronous dynamic random access memory (SDRAM) cells which fails to properly verify that the program operation was successful; and

programming access circuitry to replace the defective memory cell with an available redundant memory cell.