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Method and apparatus for computing delay correlation effects in digital circuits

  • US 6,553,550 B1
  • Filed: 03/03/2000
  • Issued: 04/22/2003
  • Est. Priority Date: 03/05/1999
  • Status: Expired due to Fees
First Claim
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1. A computer implemented method for performing a circuit timing analysis between any two paths of a timing chain using correlation information between timing relationships, including delays, setups, or holds, in a general fashion, comprising the steps of:

  • identifying the timing relationships required by the analysis, listing all possible sequences of timing relationships in the analysis, deciding to maximize one of the timing paths while minimizing the other, and then selecting the sequence which produces minimum and maximum arrival times.

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