Active pixel sensor with intra-pixel charge transfer

• US 6,555,842 B1
• Filed: 06/27/2000
• Issued: 04/29/2003
• Est. Priority Date: 01/28/1994
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Fossum, Eric R., Kemeny, Sabrina E., Mendis, Sunetra
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, Mai-Huong
• Application Number:
  US09/604,846
• Time in Patent Office: 1,036 Days
• Field of Search: 257/222, 257/232, 257/234, 257/239, 257/292, 257/294
• US Class Current: 257/59
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 27/14887 Blooming suppression
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 : Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 : comprising storage means other than floating diffusion

Abstract

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Claims

1. An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells, each of said cells comprising:

a photoreceptor, adjacent said substrate, to control accumulating photo-generated charge

a readout circuit comprising at least a buffering transistor and a selecting transistor, formed in said substrate;

a coupling section formed on said substrate adjacent said photoreceptor, having a sensing node connected to said output transistor and at least one coupling stage for transferring said photogenerated charge to said sensing node; and

wherein said transistors in said readout circuit are formed of an integrated circuit technology which is compatible with complimentary metal oxide semiconductor (CMOS) technology, formed on said substrate, said substrate being of a first conductivity type, said readout circuit comprising transistors of a first conductivity type, a well region of a second conductivity type in said substrate and plural semiconductor transistors of a second conductivity type formed in said well region.

2. An imaging device as in claim 1, further comprising a microlens layer formed on at least part of the substrate to refract light incident on an area of the substrate that includes circuitry including at least said readout circuit, to the photoreceptor.

3. An imaging device comprising a focal plane array of pixel cells, each of said pixel cells including a monolithic semiconductor integrated circuit substrate, each of said pixel cells comprising:

a photoreceptor overlying a first portion of said substrate and operating to accumulate photo-generated charge in the first portion of said substrate that underlies said photogate;

a charge transfer section, formed in said substrate adjacent said photogate, having a sensing node adjacent said photoreceptor and at least one charge coupling stage, operating to transfer charge from said first portion of said substrate to said sensing node; and

a readout circuit connected to said sensing node and to no other sensing node of any other one of said pixel cells, so that said readout circuit of each said one of said pixel cells is associated with only one photoreceptor and only one charge transfer section, said readout circuit including at least a buffering transistor and a selection transistor.

4. The imaging device of claim 3 wherein:

said sensing node of said charge transfer section stage comprises a floating node; and

said charge coupling stage comprises a transfer gate between said floating node and said photogate.

5. The imaging device of claim 4 wherein said floating node is one of:

(a) a floating diffusion, and (b) a floating gate.

6. An imaging device as in claim 3, wherein said readout circuit includes a sampling element which stores the charge received from said substrate, and a shorting element which shorts across the sampling element after the charge is read.

7. A device as in claim 6, wherein said sampling element is a capacitor and said shorting element is a shorting FET.

8. An imaging device as in claim 3, wherein said readout circuit is formed of an integrated circuit technology which is compatible with complimentary metal oxide semiconductor (CMOS) technology.

9. An imaging device, comprising:

a substrate of a type which can store optical charge therein, said substrate formed of a plurality of pixel cells, each pixel cell comprising;

an optical charge storage section, including a photoreceptor;

a charge transfer section, having a sensing node, and having a first state in which charge from the photoreceptor is isolated from the sensing node and a second state in which charge from the photoreceptor is coupled to said sensing node; and

a readout circuit, having an input connected to said sensing node, said readout circuit connected to no other nodes of any of the other pixel cells of the device so that each optical charge storage section and charge transfer section is associated with only one readout circuit.

10. A device as in claim 9, wherein said sensing node of said charge transfer section includes a first floating element, which is initially isolated from charge and is later coupled to the charge.

11. An device as in claim 10, wherein said readout circuit includes a first sampling element for sampling an initial potential on the first floating element while said charge transfer section is isolated from said first floating element, and a second sampling element for sampling a later potential on said floating element when said charge transfer section is coupled to the first floating element.

12. A device as in claim 11, wherein said readout circuit includes double sampling circuitry subtracting said initial potential from said later potential to produce a difference, and wherein an output of said readout circuit is proportional to the difference.

13. A device as in claim 12, wherein said sampling elements comprise capacitors.

14. A device as in claim 9, wherein said readout circuit includes an input node to the readout circuit which is directly connected to the sensing node of said charge transfer section, said input node including a follower circuit.

15. A device as in claim 9, further comprising a microlens layer formed on at least part of the substrate to refract light incident on an area of the substrate that includes circuitry including at least said readout circuit, to the optical charge storage section.

16. An imaging device as in claim 9, wherein said readout circuit is formed of an integrated circuit technology which is compatible with complimentary metal oxide semiconductor (CMOS) technology.

17. An imaging device, comprising:

a focal plane array of pixel cells, including a substrate of a type which can store optical charge therein;

each pixel cell formed in a predetermined area of said substrate, and comprising;

an optical charge storage section, including a photoreceptor overlying a first portion of said predetermined area of said substrate which accumulates charge therein;

a plurality of circuitry elements, formed in a second portion of said predetermined area; and

a microlens, overlying at least said second portion, and directing light impinging on said second portion to said first portion.

18. An imaging device as in claim 17, wherein said plurality of circuitry elements comprises:

a charge transfer section, having a sensing node, and having a first state in which charge in the substrate is isolated from the sensing node and a second state in which charge in the substrate is coupled to said sensing node; and

a readout circuit, having an input connected to said sensing node, said readout circuit connected to no other nodes of any of the other pixel cells of the device so that each optical charge storage section and charge transfer section is associated with only one readout circuit.

19. An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells, each one of said cells comprising:

a photosensor coupled to said substrate, and accumulating photo-generated charge in said substrate;

a readout circuit comprising at least a select transistor and a buffering transistor, formed in said substrate;

a coupling section, formed on said substrate adjacent said photgate, having a sensing node connected to said output transistor and at least one coupling stage which transfers charge from said underlying portion of said substrate to said sensing node.