Devices and methods for addressing optical edge effects in connection with etched trenches

• US 6,555,895 B1
• Filed: 07/17/2000
• Issued: 04/29/2003
• Est. Priority Date: 07/17/2000
• Status: Expired due to Fees

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/617,356
• Time in Patent Office: 1,016 Days
• Field of Search: 257/328, 257/618, 257/622, 257/626, 257/496, 257/510, 257/513, 257/521, 257/586, 257/594, 257/396-399, 716/19, 716/21
• US Class Current: 257/622
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (1) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity type in the body region adjacent to the each internal trench, but not adjacent to the at least one peripheral trench.

Claims

1. A modified semiconductor substrate comprising:

semiconductor substrate;

at least one buffer layer provided over at least a portion of said substrate; and

a plurality of trenches comprising (a) a plurality of internal trenches that extend into said semiconductor substrate and (b) at least one shallow peripheral trench that extends into said at least one buffer layer but does not extend into the semiconductor substrate,

wherein said at least one buffer layer is provided over said semiconductor substrate in the area of said at least one shallow peripheral trench and no buffer layer is provided over said semiconductor substrate in the area of said plurality of internal trenches.

2. The modified semiconductor substrate of claim 1, wherein the at least one buffer layer is an oxide layer.

3. The modified semiconductor substrate of claim 1, wherein the semiconductor substrate is a silicon substrate.

4. A trench DMOS transistor comprising the modified substrate of claim 1.

5. A DRAM device comprising the modified substrate of claim 1.

6. A modified semiconductor substrate comprising:

a semiconductor substrate;

at least one buffer layer provided over at least a portion of said substrate; and

a plurality of trenches comprising (a) a plurality of internal trenches that extend into said semiconductor substrate and (b) at least one shallow peripheral trench that extends into said at least one buffer layer but does not extend into the semiconductor substrate,

wherein the at least one buffer layer is a nitride layer.

7. A trench Schottky barrier rectifier comprising a modified semiconductor substrate, the substrate comprising:

a semiconductor substrate;

at least one buffer layer provided over at least a portion of said substrate; and

a plurality of trenches comprising (a) a plurality of internal trenches that extend into said semiconductor substrate and (b) at least one shallow peripheral trench that extends into said at least one buffer layer but does not extend into the semiconductor substrate.

8. A modified semiconductor substrate comprising

a semiconductor substrate;

at least one buffer layer provided over at least a portion of said substrate; and

a plurality of trenches comprising (a) a plurality of internal trenches that extend into said semiconductor substrate and (b) at least one shallow peripheral trench that extends into said at least one buffer layer but does not extend into the semiconductor substrate,

wherein said at least one buffer layer is provided over said semiconductor substrate in the area of said at least one shallow peripheral trench, wherein said at least one buffer layer is provided over said semiconductor substrate in the area of said plurality of internal trenches,

wherein said at least one buffer layer in the area of said plurality of internal trenches is thinner than said at least one buffer layer in the area of said at least one shallow peripheral trench,

wherein each internal trench extends through said at least one buffer layer in the area of said plurality of internal trenches and into said semiconductor substrate, and

wherein each shallow peripheral trench does not extend through said at least one buffer layer in the area of said at least one shallow peripheral trench and does not extend into said semiconductor substrate.

9. The modified semiconductor substrate of claim 8,

wherein said at least one buffer layer in the area of said plurality of internal trenches consists of a single buffer layer and

wherein said at least one buffer layer in the area of said at least one shallow peripheral trench consists of two buffer layers.

10. The modified semiconductor substrate of claim 8, wherein the at least one buffer layer is an oxide layer.

11. The modified semiconductor substrate of claim 8, wherein the semiconductor substrate is a silicon substrate.

12. A trench DMOS transistor comprising the modified substrate of claim 8.

13. A DRAM device comprising the modified substrate of claim 8.