Method and apparatus for local parameter variation compensation

• US 6,556,022 B2
• Filed: 06/29/2001
• Issued: 04/29/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: To, Thomas, Volk, Andrew M., Hsu, Jen-Tai
• Primary Examiner(s): Le, N.
• Assistant Examiner(s): LEROUX, ETIENNE PIERRE
• Application Number:
  US09/895,290
• Publication Number:
  US 20030006781A1
• Time in Patent Office: 669 Days
• Field of Search: 324/600, 324/601, 324/605, 324/606, 327/543, 327/158, 327/236, 327/362, 327/512, 327/515, 327/513, 327/530-560
• US Class Current: 324/600
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

In order to detect performance parameter variations at different locations, local parameter detectors are located at the various local locations. One of the local locations is selected as the reference location while the other local locations are selected as destination locations. The reference location is utilized to determine a reference parameter value, while each destination location compares its local parameter value to the reference parameter value. The parameter values are current encoded and the reference parameter value is sent to the other locations for the comparisons. The comparison at the destination locations each generates a corrective signal to compensate for the difference in the parameter value between the locations. Parameter compensation is provided to reduce performance skew among the distributed locations.

Claims

1. An apparatus comprising:

a first detector located at a first location to detect a reference parameter value associated with determination of process, voltage and temperature (PVT) values at the first location and to generate a first encoded signal indicative of the reference parameter value, the first encoded signal to have the PVT values encoded into an encoded analog current signal;

a second detector located at a second location to detect a local parameter value associated with determination of PVT values at the second location and to generate a second encoded signal indicative of the local parameter value; and

a comparison circuit located at the second location to receive the first and second encoded signals and to generate a corrective signal based on a difference of the local parameter value from the reference parameter value;

a compensation circuit located at the second location to use the corrective signal to correct operation of an operative circuit at the second location.

2. The apparatus of claim 1 wherein the second encoded also to have the PVT values encoded into an encoded signal analog current signal.

3. The apparatus of claim 1 wherein the compensation circuit corrects for performance skew between operative circuits located at the first and second locations.

4. The apparatus of claim 1 wherein the compensation circuit corrects for timing skew between operative circuits located at the first and second locations, in which the timing skew is caused by the variation of the PVT values at the two locations.

5. The apparatus of claim 4 wherein the timing skew is corrected by a delay circuit which increases or decreases the timing of the operative circuit at the second location based on the corrective signal.

6. A semiconductor device comprising:

a plurality of detectors distributed at various locations on a semiconductor die to detect a circuit parameter value at respective distributed locations, one of the locations identified as a reference location and others identified as destination locations, wherein the circuit parameter value at the reference location is selected as a reference parameter value, which is associated with determination of process, voltage and temperature (PVT) values at the reference location, and the circuit parameter values at the destination locations are destination parameter values associated with determination of respective PVT values at the respective destination locations, the detectors to generate respective encoded signals indicative of the respective parameter values, the encoded signal of the reference location being an encoded analog current signal;

a plurality of comparison circuits, one at the respective destination locations to receive the encoded analog current signal from the reference location and to compare it to the encoded signal at the respective destination location and to generate a corrective signal based on a difference of the respective destination parameter value from the reference parameter value;

a plurality of compensation circuits at the respective destination locations to use the corrective signal at the respective destination locations to correct operation of an operative circuit at the respective location.

7. The semiconductor device of claim 6 wherein the respective compensation circuits adjusts for performance skew between operative circuits located at the reference location and the respective destination locations.

8. The semiconductor device of claim 7 wherein the comparison circuits include differential comparators.

9. The semiconductor device of claim 7 in which the plurality of detectors, comparison circuits and compensation circuits are distributed at different regions of a wafer die where a common signal is present and the compensation is used at the respective destination locations to reduce performance skew caused by variations in the common signal.

10. The semiconductor device of claim 9 wherein one or more of the detectors includes:

a voltage detector coupled to detect changes in a supply voltage; and

a voltage to current converter coupled to the voltage detector to convert the detected change in the supply voltage into the encoded analog current, the converter also including a transistor in which its threshold voltage change is also encoded into the encoded analog current, in which the encoded analog current encodes changes noted in the supply voltage and threshold voltage to detect a circuit parameter change.

11. The semiconductor device of claim 10 in which the change of the threshold voltage of the transistor is used to detect process parameter and temperature parameter changes, and the coupled supply voltage to detect a supply voltage parameter change, the parameter changes encoded into the encoded analog current.

12. The semiconductor device of claim 11 wherein the voltage to current converter further includes a voltage controlled resistor coupled to a current mirror wherein the detected supply voltage change causes the resistor to vary its resistance which varies a current of the current mirror to encode the encoded analog current.

13. The semiconductor device of claim 10 further comprising a voltage tracking component coupled to the supply voltage and to the voltage detector to track the supply voltage for detection by the voltage detector.

14. The semiconductor device of claim 13 wherein the threshold voltage change causes the current of the current mirror to encode the encoded current.

15. A method comprising:

detecting a circuit parameter value associated with determination of process, voltage and temperature (PVT) values at a first location;

generating a first encoded signal, which encode is based on the first circuit parameter value, the first encoded signal being an encoded analog current signal;

detecting a circuit parameter value associated with determination of PVT values at a second location;

generating a second encoded signal, which encode is based on the second circuit parameter value;

transferring the first encoded signal, to the second location;

comparing the first and second encoded signals to determine a variation between the two encoded signals;

generating a corrective signal based on the comparison of the two encoded currents;

applying the corrective signal at the second location to an operative circuit to reduce performance skew between the two locations caused by differences in the parameter values at the two locations.

16. The method of claim 15 further including compensating the operative circuit at the second location by varying a signal delay to reduce the performance skew.

17. The method of claim 15 further having a plurality of second locations to compensate the performance skew at distributed locations on a semiconductor die.

18. The method of claim 15 wherein the generating a first and second encoded signal, generates both a first and second encoded analog current signals.

19. A system comprising:

a plurality of components distributed in the system and the components including;

a detector to detect a circuit parameter value at respective component locations, but with one of the components identified as a reference component and others identified as destination components, in which the circuit parameter value of the reference component is selected as a reference parameter value, which is associated with determination of process, voltage and temperature (PVT) values at the reference location, and the circuit parameter value of the destination components are destination parameter values also associated with determination of respective PVT values at the respective destination locations, the detectors to generate respective encoded signals indicative of its PVT values and in which the detector of the reference component generates an encoded analog current signal; and

a plurality of comparison circuits at the respective destination component locations to receive the encoded analog current signal from the reference component and compare it to the encoded signals at the respective destination component locations and to generate a corrective signal for each destination component based on a difference of the respective destination parameter value from the reference parameter value.

20. The system of claim 19 wherein the respective components include a compensation circuit coupled to a respective comparison circuit to adjust a common signal routed to the destination components to reduce performance skew caused by variations in the common signal in the components.