Programmable logic device including multipliers and configurations thereof to reduce resource utilization

• US 6,556,044 B2
• Filed: 09/18/2001
• Issued: 04/29/2003
• Est. Priority Date: 09/18/2001
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin, Starr, Gregory, Hwang, Chiao Kai
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/955,647
• Publication Number:
  US 20030052713A1
• Time in Patent Office: 588 Days
• Field of Search: 326/16, 326/37, 326/38, 326/39, 326/41, 714/724-727
• US Class Current: 326/40
• CPC Class Codes: G06F 2207/3816 Accepting numbers of variable word length
• CPC Class Codes: G06F 7/523 Multiplying only
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

Claims

1. A programmable logic device comprising:

a multiplier circuit;

a plurality of scan chain registers for testing said programmable logic device, at least a portion of said plurality of scan chain registers being located adjacent said multiplier circuit; and

input circuitry for inputting data in said scan chain registers into said multiplier circuit.

2. The programmable logic device of claim 1 further comprising:

a plurality of inputs for inputting bits of multiplicands to said multiplier circuit;

wherein;

said at least a portion of said plurality of scan chain registers is adjacent said plurality of inputs;

said input circuitry combines data in said inputs with data in said scan chain registers for inputting into said multiplier circuit.

3. The programmable logic device of claim 2 wherein:

said multiplier circuit is an m×

n multiplier circuit for performing multiplication of an m-bit number by an n-bit number;

said inputs comprise;

m inputs for inputting m bits of said m-bit number to said multiplier circuit, and n inputs for inputting n bits of said n-bit number to said multiplier circuit; and

said plurality of scan chain registers includes at least m+n said scan chain registers.

4. The programmable logic device of claim 3 wherein said input circuitry comprises AND circuitry for ANDing data in said inputs with data in said plurality of scan chain registers for input to said multiplier circuit.

5. The programmable logic device of claim 4 wherein:

p of said m scan chain registers adjacent said m inputs are loaded with p logic ones, and m−

p of said m scan chain registers adjacent to said m inputs are loaded with m−

p logic zeroes, where p<

m;

q of said scan n chain registers adjacent said n inputs are loaded with q logic ones, and n−

q of said n scan chain registers adjacent said n inputs are loaded with n−

q logic zeroes, where q<

n; and

said AND circuitry ANDs data in said m inputs with data in said m scan chain registers, and ANDs data in said n inputs with data in said n scan chain registers;

whereby;

said m×

n multiplier circuit is configured as a p×

q multiplier circuit.

6. The programmable logic device of claim 5 wherein:

said p logic ones are in p most significant ones of said m scan chain registers; and

said m−

p logic zeroes are in m−

p least significant ones of said m scan chain registers.

7. The programmable logic device of claim 6 wherein:

said q logic ones are in q most significant ones of said n scan chain registers; and

said n−

q logic zeroes are in n−

q least significant ones of said n scan chain registers.

8. The programmable logic device of claim 5 wherein:

said q logic ones are in q most significant ones of said n scan chain registers; and

said n−

q logic zeroes are in n−

q least significant ones of said n scan chain registers.

9. The programmable logic device of claim 2 wherein said input circuitry comprises AND circuitry for ANDing data in said inputs with data in said plurality of scan chain registers for input to said multiplier circuit.

10. The programmable logic device of claim 2 wherein:

said plurality of inputs comprises a plurality of input registers for inputting bits of multiplicands to said multiplier circuit;

said at least a portion of said plurality of scan chain registers is adjacent said plurality of input registers;

said input circuitry combines data in said input registers with data in said scan chain registers for inputting into said multiplier circuit.

11. The programmable logic device of claim 10 wherein:

said multiplier circuit is an m×

n multiplier circuit for performing multiplication of an m-bit number by an n-bit number;

said input registers comprise;

m registers for inputting m bits of said m-bit number to said multiplier circuit, and

n registers for inputting n bits of said n-bit number to said multiplier circuit; and

said plurality of scan chain registers includes at least m+n said scan chain registers.

12. The programmable logic device of claim 11 wherein said input circuitry comprises AND circuitry for ANDing data in said input registers with data in said plurality of scan chain registers for input to said multiplier circuit.

13. The programmable logic device of claim 12 wherein:

p of said m scan chain registers adjacent said m input registers are loaded with p logic ones, and m−

p of said m scan chain registers adjacent said m input registers are loaded with m−

p logic zeroes, where p<

m;

q of said scan n chain registers adjacent said n input registers are loaded with q logic ones, and n−

q of said n scan chain registers adjacent said n input registers are loaded with n−

q logic zeroes, where q<

n; and

said AND circuitry ANDs data in said m input registers with data in said m scan chain registers, and ANDs data in said n input registers with data in said n scan chain registers;

whereby;

said m×

n multiplier circuit is configured as a p×

q multiplier circuit.

14. The programmable logic device of claim 13 wherein:

said p logic ones are in p most significant ones of said m scan chain registers; and

said m−

p logic zeroes are in m−

p least significant ones of said m scan chain registers.

15. The programmable logic device of claim 14 wherein:

said q logic ones are in q most significant ones of said n scan chain registers; and

said n−

q logic zeroes are in n−

q least significant ones of said n scan chain registers.

16. The programmable logic device of claim 13 wherein:

said q logic ones are in q most significant ones of said n scan chain registers; and

said n−

q logic zeroes are in n−

q least significant ones of said n scan chain registers.

17. The programmable logic device of claim 10 wherein said input circuitry comprises AND circuitry for ANDing data in said input registers with data in said plurality of scan chain registers for input to said multiplier circuit.

18. The programmable logic device of claim 1 wherein:

said multiplier circuit comprises a first input for inputting bits of a first multiplicand and a second input for inputting bits of a second multiplicand; and

said at least a portion of said plurality of scan chain registers is connected to one of said first and second inputs of said multiplier circuit;

whereby;

data loaded into said at least a first portion of said plurality of scan chain registers after said testing represent at least one of said first and second multiplicands.

19. The programmable logic device of claim 18 wherein:

said data representing said first multiplicand are substantially fixed during a plurality of multiplication operations.

20. The programmable logic device of claim 19 wherein:

said at least a portion of said plurality of scan chain registers representing said first multiplicand is clocked by a separate clock from others of said plurality of scan chain registers;

whereby;

said first multiplicand is kept substantially fixed by stopping said separate clock.

21. The programmable logic device of claim 20 wherein said separate clock is restarted to change said first multiplicand during operation of said programmable logic device.

22. The programmable logic device of claim 19 further comprising:

a switch for separating said at least a portion of said plurality of scan chain registers representing said first multiplicand from others of said plurality of scan chain registers;

whereby;

said first multiplicand is kept substantially fixed by opening said switch.

23. The programmable logic device of claim 22 wherein said switch is closed to change said first multiplicand during operation of said programmable logic device.

24. The programmable logic device of claim 19 comprising:

a plurality of said multiplier circuits arranged in a logic block, each said multiplier circuit having one said first multiplicand and one said second multiplicand;

said logic block further comprising;

a plurality of adders for accumulating outputs of said plurality of said multiplier circuits.

25. The programmable logic device of claim 24 wherein:

said multipliers and said adders in said logic block are adapted to be configured to form a finite impulse response filter; and

each said first multiplicand represents a coefficient of said finite impulse response filter.

26. The programmable logic device of claim 25 wherein:

said logic block comprises four said multiplier circuits and three said adders;

a first of said adders adds outputs of a first and second of said multiplier circuits;

a second of said adders adds outputs of a third and fourth of said multiplier circuits; and

a third of said adders adds outputs of said first and second adders.

27. The programmable logic device of claim 26 further comprising a plurality of registers for registering data in said finite impulse response filter.

28. The programmable logic device of claim 27 wherein said plurality of registers are chained on an input to said logic block, each said register providing an output for input to one said multiplier circuit.

29. The programmable logic device of claim 25 wherein said logic block comprises a number of said multiplier circuits and a number of said adders equal to said number of said multiplier circuits, each said adder adding an output of one said multiplier circuits to a previous sum.

30. The programmable logic device of claim 29 wherein a first said previous sum is an input to said logic block.

31. The programmable logic device of claim 30 further comprising a plurality of registers for registering data in said finite impulse response filter.

32. The programmable logic device of claim 31 wherein each said register registers an output of one of said adders, each said registered output forming one of said previous sums.

33. The programmable logic device of claim 29 further comprising a plurality of registers for registering data in said finite impulse response filter.

34. The programmable logic device of claim 33 wherein each said register registers an output of one of said adders, each said registered output forming one of said previous sums.

35. The programmable logic device of claim 19 wherein registers in said at least a first portion of said plurality of scan chain registers representing said first multiplicand are prevented from further input after said loading.

36. The programmable logic device of claim 35 wherein said registers in said at least a first portion of said plurality of scan chain registers representing said first multiplicand are prevented from further input after said loading by grounding of a first clock.

37. The programmable logic device of claim 36 wherein registers in said at least a first portion of said plurality of scan chain registers representing said second multiplicand receive further input after said loading by clocking of a second clock different from said first clock.

38. The programmable logic device of claim 35 wherein said registers in said at least a portion of said plurality of scan chain registers representing said first multiplicand are prevented from further input after said loading by opening of a connection to said registers representing said first multiplicand.

39. The programmable logic device of claim 38 wherein said registers in said at least a first portion of said plurality of scan chain registers representing said second multiplicand continue to receive further input after said opening of said connection.

40. The programmable logic device of claim 39 comprising:

a plurality of said multiplier circuits arranged in a logic block, each said multiplier circuit having one said first multiplicand and one said second multiplicand;

said logic block further comprising;

a plurality of adders for accumulating outputs of said plurality of said multiplier circuits.

41. The programmable logic device of claim 40 wherein:

said multipliers and said adders in said logic block are adapted to be configured to form a finite impulse response filter; and

each said first multiplicand represents a coefficient of said finite impulse response filter.

42. The programmable logic device of claim 41 wherein:

said logic block comprises four said multiplier circuits and three said adders;

a first of said adders adds outputs of a first and second of said multiplier circuits;

a second of said adders adds outputs of a third and fourth of said multiplier circuits; and

a third of said adders adds outputs of said first and second adders.

43. The programmable logic device of claim 42 further comprising a plurality of registers for registering data in said finite impulse response filter.

44. The programmable logic device of claim 43 wherein said plurality of registers are chained on an input to said logic block, each said register providing an output for input to one said multiplier circuit.

45. The programmable logic device of claim 41 wherein said logic block comprises a number of said multiplier circuits and a number of said adders equal to said number of said multiplier circuits, each said adder adding an output of one said multiplier circuits to a previous sum.

46. The programmable logic device of claim 45 wherein a first said previous sum is an input to said logic block.

47. The programmable logic device of claim 46 further comprising a plurality of registers for registering data in said finite impulse response filter.

48. The programmable logic device of claim 47 wherein each said register registers an output of one of said adders, each said registered output forming one of said previous sums.

49. The programmable logic device of claim 45 further comprising a plurality of registers for registering data in said finite impulse response filter.

50. The programmable logic device of claim 49 wherein each said register registers an output of one of said adders, each said registered output forming one of said previous sums.

51. The programmable logic device of claim 41 further comprising a plurality of registers for registering data in said finite impulse response filter.

63. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.

64. A printed circuit board on which is mounted a programmable logic device as defined in claim 1.

65. The printed circuit board defined in claim 64 further comprising:

a memory mounted on the printed circuit board and coupled to the programmable logic device.

66. The printed circuit board defined in claim 65 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the memory.

67. The printed circuit board defined in claim 66 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

52. A programmable logic device comprising:

a plurality of multiplier circuits arranged in a logic block, each said multiplier circuit having a first multiplicand and a second multiplicand;

said logic block further comprising;

a plurality of adders for accumulating outputs of said plurality of multiplier circuits;

wherein;

said multipliers and said adders in said logic block are adapted to be configured to form a finite impulse response filter.

53. The programmable logic device of claim 52 wherein:

said logic block comprises four said multiplier circuits and three said adders;

a first of said adders adds outputs of a first and second of said multiplier circuits;

a second of said adders adds outputs of a third and fourth of said multiplier circuits; and

a third of said adders adds outputs of said first and second adders.

54. The programmable logic device of claim 53 further comprising a plurality of registers for registering data in said finite impulse response filter.

55. The programmable logic device of claim 54 wherein said plurality of registers are chained on an input to said logic block, each said register providing an output for input to one said multiplier circuit.

56. The programmable logic device of claim 52 wherein said logic block comprises a number of said multiplier circuits and a number of said adders equal to said number of said multiplier circuits, each said adder adding an output of one said multiplier circuits to a previous sum.

57. The programmable logic device of claim 56 wherein a first said previous sum is an input to said logic block.

58. The programmable logic device of claim 57 wherein said input to said logic block is an output of another said logic block.

59. The programmable logic device of claim 57 further comprising a plurality of registers for registering data in said finite impulse response filter.

60. The programmable logic device of claim 59 wherein each said register registers an output of one of said adders, each said registered output forming one of said previous sums.

61. The programmable logic device of claim 52 further comprising a plurality of registers for registering data in said finite impulse response filter.

62. The programmable logic device of claim 52 wherein each said first multiplicand represents a coefficient of said finite impulse response filter.

68. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 52 coupled to the processing circuitry and the memory.

69. A printed circuit board on which is mounted a programmable logic device as defined in claim 52.

70. The printed circuit board defined in claim 69 further comprising:

a memory mounted on the printed circuit board and coupled to the programmable logic device.

71. The printed circuit board defined in claim 70 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the memory.

72. The printed circuit board defined in claim 71 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.