Half-bridge gate driver optimized for hard-switching

• US 6,556,053 B2
• Filed: 02/06/2002
• Issued: 04/29/2003
• Est. Priority Date: 02/06/2001
• Status: Expired due to Term

• Current Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Stanley, Gerald R
• Primary Examiner(s): Vu, Bao Q.
• Application Number:
  US10/068,271
• Publication Number:
  US 20020125920A1
• Time in Patent Office: 447 Days
• Field of Search: 323/222, 318/293, 318/599, 327/108, 327/109, 327/382
• US Class Current: 327/108
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2017/6875 using self-conductive, depletion FETs

Abstract

A half-bridge gate driver circuit including two separate floating high-side driver circuits for operating a switch circuit having a high-side switch and a low-side switch. Each of the driver circuits include input control logic which is referenced to a supply signal with a potential that becomes negative relative to the negative common terminal of the switches, thereby enhancing the operation of the switch circuit. The circuit may further include signal translation stages for translating control signals to the control logic of the driver circuits. The signal translation stages include a plurality of cascoded parasitic transistors which provide a neutralizing capacitance to minimize noise.

Claims

1. A gate driver circuit for a half-bridge derived switching power converter having a high-side switch coupled to a negative potential and a low-side switch coupled to the negative potential, the gate driver circuit comprising:

a first high-side driver circuit referenced to a common potential, the first high-side driver circuit capable of driving the high-side switch to produce a first output; and

a second high-side driver circuit referenced to the common potential, the second high-side driver circuit capable of driving a low-side switch to produce a second output,

where the common potential remains more negative than the first output.

2. The gate driver circuit of claim 1, where the common potential is selectively provided with one of the negative potential and the first output as a function of the voltage magnitude of the first output.

3. The gate driver circuit of claim 1, where the common potential is selectively provided with one of the negative potential and a charge pump driven by an AC source.

4. The gate driver circuit of claim 1, where signal propagation delay through the first and second high-side driver circuits is substantially the same.

5. The gate driver circuit of claim 1, where control signals provided to the first and second high-side driver circuits are isolated from each other to minimize noise derived from switching.

6. The gate driver circuit of claim 1, further comprising a signal translation stage coupled with at least one of the first and second high-side driver circuits, where the signal translation stage includes a plurality of cascaded common base stages and a buffer, the signal translation stage operable to translate the reference of an input signal to the common potential.

7. The gate driver circuit claim 6, where the signal translation stage includes a parasitic transistor coupled with one of the common base stages, the parasitic transistor operable to inject noise compensation into the translated input signal.

8. The gate driver circuit of claim 6, where the signal translation stage is operable as a voltage divider to translate PWM signals.

9. The gate claim 6, where driver each of the common base stages includes a transistor and a capacitor, where the capacitor is operable to provide noise reduction.

10. The gate driver circuit of claim 6, where all but one of the common base stages include a transistor having a base node that is bypassed to ground potential, the remaining common base stage includes a transistor that is coupled with the common potential through a resistor.

11. The gate driver circuit of claim 6, where at least one of the first and second high-side driver circuits are capable of driving the respective high-side and low-side switches as a function of the translated input signal provided by the signal translation stage.

12. A gate driver circuit for a half-bridge derived switching power converter having a first switch coupled to a negative potential and a positive potential that define a potential range therebetween, and a second switch also coupled to the positive and negative potentials, the gate driver circuit comprising:

a first high-side driver circuit capable of operating the first switch; and

a second high-side driver circuit capable of operating the second switch;

where the first and second high-side driver circuits are supplied with a power input that is referenced to a common potential, the common potential is dynamically adjustable to be outside the potential range when an output of the first switch becomes more negative than the negative potential.

13. The gate driver circuit of claim 12, where the common potential is substantially the same as the negative potential when the output of the first switch is more positive than the negative potential.

14. The gate driver circuit of claim 12, where the common potential is pulled down to be substantially the same as the output of the first switch when the output of the first switch is more negative than the negative potential.

15. The gate driver circuit of claim 12, where the common potential is dynamically adjustable as a function of a transient excursion of the first switch during turn off.

16. The gate driver circuit of claim 12, further comprising a first and second translation stage coupled with the first and second high-side driver circuits, respectively, where each of the first and second translation stages includes a plurality of cascaded transistors and a parasitic transistor coupled with one of the cascaded transistors.

17. The gate driver circuit of claim 12, where the parasitic transistor is operable to provide charging currents to cancel the noise formed in the translation stage by at least one of the common potential and the negative potential.

18. The gate driver circuit of claim 12, where input signals are propagated through substantially identical logic in the first high-side driver circuit and the second high-side driver circuit.

19. The gate driver circuit of claim 12, where both the first and the second high-side driver circuits include a pulse generator and a receiving stage.

20. A half-bridge derived switching power converter comprising:

a high-side switch having an output, where the output of the high-side switch is coupled with a negative supply voltage;

a low-side switch having an output, where the output of the low-side switch is coupled with a positive supply voltage, and also inductively coupled with the output of the high-side switch;

a first high-side driver circuit operable to drive the high-side switch as a function of an input signal;

a second high-side driver circuit operable to drive the low-side switch as a function of an input signal; and

a reference supply voltage supplied to the first and second high-side driver circuits, where the reference supply voltage remains more negative than the output of the high-side switch.

21. The half-bridge derived switching power converter of claim 20, further comprising a signal translation stage coupled between the input signal and an input of at least one of the first and second high-side driver circuits, the signal translation stage operable to translate the input signal to the potential of the reference supply voltage.

22. The half-bridge derived switching power converter of claim 21, where the translation stage includes three or more cascaded transistors each with a base node bypassed to earth ground through a capacitor.

23. The half-bridge derived switching power converter of claim 21, where the translation stage includes a parasitic transistor operable to cancel the effects of noise induced by at least one of the reference supply voltage and the negative supply voltage.

24. The half-bridge derived switching power converter of claim 20, where the first and second high-side driver circuits are operable with separate and isolated input signals.

25. The half-bridge derived switching power converter of claim 20, where the high-side and low-side switches are part of an opposed current power converter.

26. The half-bridge derived switching power converter of claim 20, where the high-side switch includes a diode coupled between the first output and the negative supply voltage, the reference supply voltage being selectively representative of rectification of the forward voltage across the diode when the high-side switch is first opened.

27. The half-bridge derived switching power converter of claim 20, further comprising a first diode coupled between the negative supply voltage and a second diode, the second diode coupled between the first diode and an output of the high-side switch, where the reference supply voltage is selectively provided with one of the negative supply voltage and the voltage at the output of the high-side switch as a function of the first and second diodes.

28. The half-bridge derived switching power converter of claim 20, further comprising an AC supply, where the reference supply voltage is selectively provided with one of the AC supply and the negative supply voltage.