Differential amplifying circuit and multi-stage differential amplifying circuit using the same

• US 6,556,074 B2
• Filed: 04/23/2002
• Issued: 04/29/2003
• Est. Priority Date: 04/27/2001
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Suzuki, Yasufumi
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/127,877
• Publication Number:
  US 20020158685A1
• Time in Patent Office: 371 Days
• Field of Search: 327/563, 327/562, 327/434, 327/50, 327/52
• US Class Current: 327/563
• CPC Class Codes: H03F 2203/45364 the AAC comprising multiple transistors parallel coupled at their gates and sources only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45652 the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
• CPC Class Codes: H03F 2203/45691 the LC comprising one or more transistors as active loading resistors
• CPC Class Codes: H03F 2203/45694 the LC comprising more than one shunting resistor
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45739 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03F 3/45757 by using a feedforward circuit

Abstract

A multi-stage differential amplifying circuit (100) is disclosed. Multi-stage differential amplifying circuit (100) may include initial stage differential amplifying circuits (SN1 and SP1). Initial stage amplifying circuits (SN1 and SP1) may receive an input signal at input terminals (H01 and H02) and provide a differential output signal at nodes (N9 and N13). An amplitude controlling transistor (ND) may provide a controllable impedance path between nodes (N9 and N13). Amplitude controlling transistor (ND) may have a control gate connected to a current supply node (N10). The controllable impedance path may be controlled so that a magnitude of a differential output signal at nodes (N9 and N13) may be more consistent even when an offset voltage of an input signal at input terminals (H01 and H02) varies. A next stage differential amplifying circuit (SOP) may receive the differential output signal at nodes (N9 and N13) and provide an output signal at an output terminal (N01).

Claims

1. A differential amplifying circuit, comprising:

first and second input terminals coupled to receive an input signal;

a current source coupled between a power supply and a current supplying terminal;

an amplitude controlling transistor providing a controllable impedance path between a forward and a reverse output terminal of a differential amplifying stage and having a gate coupled to the current supplying terminal.

2. The differential amplifying circuit according to claim 1, further including:

a first input transistor having a gate coupled to the first input terminal;

a second input transistor having a gate coupled to the second input terminal wherein

the first and second input transistors are insulated gate field effect transistors (IGFETs) having a first conductivity type and the amplitude controlling transistor is an IGFET having a second conductivity type.

3. The differential amplifying circuit according to claim 2, wherein:

the first conductivity type is a p-type and the second conductivity type is an n-type.

4. The differential amplifying circuit according to claim 2, wherein:

the first conductivity type is an n-type and the second conductivity type is a p-type.

5. The differential amplifying circuit according to claim 2, wherein:

the forward and reverse output signals are provided as an input to a next stage circuit including at least one transistor having a first gate oxide thickness; and

the first and second input transistors have a second gate oxide thickness that is thicker than the first gate oxide thickness.

6. The differential amplifying circuit according to claim 1, wherein:

the differential amplifying circuit is included in an input buffer circuit on an integrated circuit.

7. A multi-stage differential amplifying circuit, comprising:

a first differential amplifying circuit coupled to receive an input signal at first and second input terminals and provides a differential output signal at a forward and a reverse output terminal, the first differential amplifying circuit includes a first input transistor having a gate coupled to the first input terminal and a second input transistor having a gate coupled to the second input terminal;

a current source coupled between a first power supply and a current supply node and the current supply node provides current to the first and second input transistors;

an amplitude controlling transistor having a gate coupled to the current supply node and providing a controllable impedance path between the forward and a reverse output terminals; and

a second differential amplifying circuit coupled to receive the differential output signal and provide a multi-stage output signal.

8. The multi-stage differential amplifying circuit according to claim 7, wherein:

the first and second input transistors are insulated gate field effect transistors (IGFETs) having a first conductivity type and the amplitude controlling transistor is an IGFET having a second conductivity type.

9. The multi-stage differential amplifying circuit according to claim 8, further including:

the first conductivity type is a p-type and the second conductivity type is an n-type.

10. The multi-stage differential amplifying circuit according to claim 8, wherein:

the first conductivity type is an n-type and the second conductivity type is a p-type.

11. The multi-stage differential amplifying circuit according to claim 8, wherein:

the second differential amplifying circuit includes at least one IGFET having a first gate oxide thickness;

the first and second input transistors have a second gate oxide thickness that is thicker than the first gate oxide thickness.

12. The multi-stage differential amplifying circuit according to claim 7, wherein:

the second differential amplifying circuit is coupled to operate from a second power supply; and

the second power supply has a lower potential than the first power supply.

13. The multi-stage differential amplifying circuit according to claim 7, wherein:

the multi-stage differential amplifying circuit is included in an input buffer circuit on an integrated circuit.

14. A differential amplifying circuit, comprising:

first and second input terminals,

a first differential amplifying circuit coupled to receive a differential input signal from the first and second input terminals and provide a differential output signal at a forward and a reverse output terminal; and

an amplitude controlling insulated gate field effect transistor (IGFET) providing a controllable impedance path between the forward and reverse output terminals wherein

a potential at a control gate of the amplitude controlling IGFET varies as an offset voltage of the differential input signal varies.

15. The differential amplifying circuit according to claim 14, wherein:

an impedance of the controllable impedance path is lower when the offset voltage is a first potential than when the offset voltage is a second potential.

16. The differential amplifying circuit according to claim 15, wherein:

the first potential is higher than the second potential.

17. The differential amplifying circuit according to claim 14, wherein:

the first differential amplifying circuit includes a first input IGFET having a first control gate coupled to the first input terminal and a second input IGFET having a second control gate coupled to the second input terminal; and

the first and second IGFETs have a p-type conductivity and the amplitude controlling IGFET has an n-type conductivity.

18. The differential amplifying circuit according to claim 14, wherein:

the first differential amplifying circuit includes a first input IGFET having a first control gate coupled to the first input terminal and a second input IGFET having a second control gate coupled to the second input terminal; and

the first and second IGFETs have a n-type conductivity and the amplitude controlling IGFET has a p-type conductivity.

19. The differential amplifying circuit according to claim 14, further including:

a second differential amplifying circuit coupled to receive the differential output signal and provide a multi-stage output signal.

20. The differential amplifying circuit according to claim 19, wherein:

the first differential amplifying circuit is coupled to operate from a first power supply and the second differential amplifying circuit is coupled to operate from a second power supply and the first power supply has a higher potential than the second power supply.