Residue-compensating A/D converter

• US 6,556,158 B2
• Filed: 03/05/2001
• Issued: 04/29/2003
• Est. Priority Date: 01/19/1999
• Status: Expired due to Term

• Current Assignee: Analog Devices BV (Analog Devices, Inc.)
• Original Assignee: Esion, LLC
• Inventors: Steensgaard-Madsen, Jesper
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US09/694,063
• Publication Number:
  US 20020041247A1
• Time in Patent Office: 785 Days
• Field of Search: 341/118, 341/120, 341/131, 341/143, 341/155, 341/156, 348/574
• US Class Current: 341/131
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 3/416 all these quantisers being multiple bit quantisers

Abstract

An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero. An analog compensation signal, m0, which is described by a well-controlled relationship to the residue signal, r0, is extracted from the filter [158]. Ideally, the closed-loop signal transfer function from g to m0 will be zero, or at least small in the signal band. A second quantizer [160] converts the analog compensation signal, m0, into a second digital signal, dm0(k). The two digital signals, d0(k) and dm0(k), are filtered individually and then added to form the overall output signal, d_g(k). The second digital filter [164] has a low signal-band gain, which implies that the sensitivity to signal-band errors caused by the second quantizer [160] will be low. The output signal, d_g(k), is a highly-accurate high-resolution representation of the input signal, g. Circuit imperfections, such as mismatch, gain errors, and nonlinearities, will cause only noise-like errors having a very low spectral power density in the signal band.

The invention facilitates the implementation of uncalibrated highly-linear high-resolution wide-bandwidth A/D converters [50D], e.g., for use in digital communication systems, such as xDSL modems and other demanding consumer-market products for which low cost is of the essence.

Claims

1. A method for converting an analog input signal to a digital output signal comprising the steps of:

(a) generating a first digital signal comprising a signal component representing a combination of said analog input signal and a dithering signal;

(b) generating an analog feedback signal by digital-to-analog converting said first digital signal;

(c) generating an analog residue signal by combining said analog input signal and said analog feedback signal;

(d) generating an analog compensation signal using a method comprising the step of processing said residue signal with a first analog filter of at least zeroth order;

(e) generating said dithering signal using a method comprising the step of processing said analog residue signal with a second analog filter;

the order said second analog filter is at least one higher than the order of said first analog filter;

(f) generating a second digital signal comprising a signal component representing said analog compensation signal; and

(g) generating said digital output signal by combining said first digital signal and said second digital signal.

2. The analog-to-digital conversion method of claim 1 wherein the step of generating said analog feedback signal comprises the steps of:

(a) generating a thermometer-coded representation of said first digital signal;

(b) generating a digital selector signal;

(c) generating a second representation of said first digital signal by permuting said thermometer-coded representation according to said digital selector signal;

(d) generating said analog feedback signal by separately digital-to-analog converting each bit in said second representation of said first digital signal.

3. The analog-to-digital conversion method of claim 2 wherein the step of generating said digital selector signal comprises the step of:

(a) calculating for a segment of said digital selector signal the running sum of the first digital signal modulo the number of bits in the thermometer-coded representation thereof.

4. The analog-to-digital conversion method of claim 2 wherein the selector signal is a random or at least pseudo-random signal.

5. The analog-to-digital conversion method of claim 1 wherein the step of generating said analog feedback signal comprises the step of:

(a) providing a mismatch-shaping digital-to-analog converter.

6. The analog-to-digital conversion method of claim 1 wherein the step of generating said dithering signal comprises the step of:

(a) generating a random or at least pseudo-random signal.

7. The analog-to-digital conversion method of claim 1 wherein the step of generating said dithering signal comprises the step of:

(a) providing a switched-capacitor filter.

8. The analog-to-digital conversion method of claim 1 wherein said first analog filter provides amplification which is essentially independent of frequency.

9. The analog-to-digital conversion method of claim 1 wherein the step of generating said second digital signal comprises the step of providing a pipeline analog-to-digital converter.

10. The analog-to-digital conversion method of claim 1 wherein the step of generating said second digital signal comprises the step of providing an analog-to-digital converter comprising a negative-feedback loop.

11. The analog-to-digital conversion method of claim 1 wherein said analog residue signal is a continuous-time signal.

12. The analog-to-digital conversion method of claim 1 wherein said first analog filter is embodied in said second analog filter.

13. The analog-to-digital conversion method of claim 1 wherein said first analog filter is a first-order integrating circuit.

14. The analog-to-digital conversion method of claim 1 wherein the step of generating said analog residue signal comprises the step of:

(a) combining at least two charge-transfer signals.

15. The analog-to-digital conversion method of claim 1 wherein the step of generating said digital output signal comprises the steps of:

(a) generating a digital residue signal by processing said second digital signal with a digital filter;

(b) adjusting said digital filter'"'"'s transfer function such that said digital residue signal is a digital representation of a difference between said analog input signal and said first digital signal.

16. The analog-to-digital conversion method of claim 1 wherein the order of said first analog filter is at most two.

17. The analog-to-digital conversion method of claim 1 wherein said second analog filter emphasizes in a selected frequency band the spectral components of said analog residue signal;

said selected frequency band being characterized by a particularly good equivalence of said analog input signal and said digital output signal.

18. The analog-to-digital conversion method of claim 1 wherein said analog compensation signal is essentially uncorrelated to said analog input signal.

19. The analog-to-digital conversion method of claim 1 wherein the step of generating said analog compensation signal comprises the step of:

(a) combining the analog feedback signal and the signal provided by the first analog filter.

20. The analog-to-digital conversion method of claim 1 wherein the step of generating said analog compensation signal comprises the step of:

(a) combining the analog input signal and the signal provided by the first analog filter.

21. The analog-to-digital conversion method of claim 1 wherein the step of generating said digital output signal comprises the step of:

(a) filtering said second digital signal with a finite-impulse-response filter having at least two non-zero coefficients.

22. The analog-to-digital conversion method of claim 1 wherein the transfer function defined from said analog input signal to said analog residue signal has a high-pass characteristic.

23. An analog-to-digital converter circuit receiving an analog input signal and providing a digital output signal comprising:

(a) a first quantizer circuit generating a first digital signal representing a combination of said analog input signal and a dithering signal;

(b) a digital-to-analog converter receiving said first digital signal and generating an analog feedback signal;

(c) a first analog filter circuit of at least zeroth order having at least one first-named input terminal and providing an analog compensation signal;

said first-named input terminal receiving a signal representing a combination of said analog input signal and said analog feedback signal;

(d) a second analog filter circuit of at least first order having at least one second-named input terminal and generating said dithering signal;

said second-named input terminal being connected to said first analog filter circuit;

(e) a second quantizer circuit receiving said analog compensation signal and generating a digital compensation signal;

(f) an output-stage digital circuit combining the first digital signal and the digital compensation signal to generate said digital output signal.

24. The analog-to-digital converter circuit of claim 23 wherein said first quantizer circuit comprises:

(a) a flash quantizer having a first third-named input terminal of a first polarity and a second fourth-named input terminal of the opposite polarity;

said third-named input terminal receiving said analog input signal;

said fourth-named input terminal receiving the negative of said dithering signal.

25. The analog-to-digital converter circuit of claim 24 wherein said flash quantizer further comprises:

(a) a resistor ladder conducting an essentially constant current;

said resistor ladder being connected to said fourth-named input terminal and is providing a set of voltage signals which are in a predetermined relationship to said fourth-named input terminal'"'"'s potential.

26. The analog-to-digital converter circuit of claim 25 wherein said resistor ladder comprises an variable impedance element, the impedance of which is controlled by a random signal;

said random signal is of an at least pseudo-random nature.

27. The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter is based on a mismatch-shaping algorithm of at least zeroth order.

28. The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter is based on a idle-tone-free mismatch-shaping algorithm of at least first order.

29. The analog-to-digital converter circuit of claim 23 further comprising:

(a) a circuit generating a first random signal of an at least pseudo-random nature;

said random signal being partially correlated with said dithering signal.

30. The analog-to-digital converter circuit of claim 23 wherein the transfer function defined from said first-named input terminal to said analog compensation signal, when said analog feedback signal is zero, is of at most second order.

31. The analog-to-digital converter circuit of claim 23 wherein said second quantizer circuit is a pipeline analog-to-digital converter.

32. The analog-to-digital converter circuit of claim 23 wherein said second quantizer circuit comprises a noise-shaping loop.

33. The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit processes a continuous-time signal.

34. The analog-to-digital converter circuit of claim 23 wherein the transfer function from said analog input signal to said analog compensation signal has a high-pass characteristic.

35. The analog-to-digital converter circuit of claim 23 further comprising:

(a) an analog front-end circuit providing said analog input signal;

said analog analog front-end circuit having a high-pass characteristic.

36. The analog-to-digital converter circuit of claim 23 employed in a digital communication system.

37. The analog-to-digital converter circuit of claim 23 comprising:

(a) at least one digital-to-analog converter having a smooth impulse response.

38. The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter has a deliberately-delayed impulse response.

39. The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter'"'"'s effective delay is at least eighty percent of the clock period.

40. The analog-to-digital converter circuit of claim 23 wherein said digital-to-analog converter is calibrated.

41. The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit is calibrated.

42. The analog-to-digital converter circuit of claim 23 wherein said dithering signal largely is virtually uncorrelated to said analog input signal.

43. The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit further comprises:

(a) a third-named input terminal receiving a signal which is essentially equivalent to the analog feedback signal.

44. The analog-to-digital converter circuit of claim 23 wherein said first analog filter circuit further comprises:

(a) a third-named input terminal receiving a signal which is essentially equivalent to the analog input signal.

45. The analog-to-digital converter circuit of claim 23 wherein said second analog filter circuit comprises switches.

46. The analog-to-digital converter circuit of claim 23 wherein said output-stage digital circuit delays said first digital signal.

47. The analog-to-digital converter circuit of claim 23 wherein said output-stage digital circuit filters said digital compensation signal with a finite-impulse-response filter.

48. The analog-to-digital converter circuit of claim 23 wherein said output-stage digital circuit is adaptive.