Dual mode signal processing system for video and still image data

• US 6,556,242 B1
• Filed: 06/16/2000
• Issued: 04/29/2003
• Est. Priority Date: 11/03/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jones, Thomas C., Corum, Curt, Dunton, Randy R., Booth, Lawrence A. Jr., Metz, Werner, Acharya, Tinku
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US09/595,055
• Time in Patent Office: 1,047 Days
• Field of Search: H04/N.5225, 348/220, 348/221, 348/222, 348/384, 348/390, 348/399, 348/420, 348/426, 348/552, 348/207
• US Class Current: 348/220.1
• CPC Class Codes: H04N 1/00204 with a digital computer or a digital computer system, e.g. an internet server programmed control between transmitter and receiver or between image input and image output device H04N1/32561
• CPC Class Codes: H04N 1/2112 using still video cameras
• CPC Class Codes: H04N 1/212 Motion video recording combined with still video recording television signal recording H04N5/76
• CPC Class Codes: H04N 1/41 Bandwidth or redundancy reduction by scanning H04N1/17 ; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 2201/0049 By wire, cable or the like
• CPC Class Codes: H04N 23/661 Transmitting camera control signals through networks, e.g. control via the Internet
• CPC Class Codes: H04N 23/959 by adjusting depth of field during image capture, e.g. maximising or setting range based on scene characteristics
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

An electronic system including signal processing circuitry that can operate in video and still image modes. Incoming image data is processed and compressed according to the operating mode. Processing includes scaling logic configured to use scaling methodologies appropriate to each mode. Compressing includes using compression methodologies appropriate to each mode.

Claims

1. An image processing system comprising:

signal processing circuitry that is configurable to operate in one of at least two modes to yield video and still image data, the processing circuitry including scaling logic for spatially scaling image data related to sensor signals into scaled image data, and

compression logic for compressing the scaled image data into compressed image data,

wherein in the first mode, the scaling logic is configured to scale according to a first scaling methodology suitable for generating video image data, and the compression logic is configured to compress according to a first compression methodology suitable for generating video image data, and

wherein in the second mode, the scaling logic is configured to scale according to a second scaling methodology suitable for generating still image data, and the compression logic is configured to compress the scaled image data according to a second compression methodology suitable for generating still image data.

2. The image processing system of claim 1 further comprising:

a compression look-up table for providing information to the compression logic, as specified by the first and second methodologies.

3. The image processing system of claim 2 further comprising:

a data packing unit for packing the compressed data into packed image data having a predefined and constant size.