Apparatus and method for an integrated photodiode in an infrared receiver

• US 6,556,330 B2
• Filed: 03/04/2002
• Issued: 04/29/2003
• Est. Priority Date: 03/10/1998
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Integration Associates, Inc. (Silicon Laboratories Incorporated)
• Inventors: Holcombe, Wayne T.
• Primary Examiner(s): Chan, Jason
• Assistant Examiner(s): Bello, Agustin
• Application Number:
  US10/090,323
• Publication Number:
  US 20020089729A1
• Time in Patent Office: 421 Days
• Field of Search: 359/189, 359/337-349, 250/201.1
• US Class Current: 398/202
• CPC Class Codes: H04B 10/114 Indoor or close-range type systems
• CPC Class Codes: H04B 10/40 Transceivers

Abstract

A method and apparatus are shown for integrating a photodiode and a receiver circuit on a single substrate. An input signal is received with the photodiode. The receiver circuit is configured to suppress feedback from an output terminal of the receiver circuit to the photodiode by amplifying the input signal to produce an amplified input signal, controlling the gain of the input signal amplification responsive to the magnitude of the amplified input signal, comparing the amplified input signal to a detection threshold voltage to produce a digital data signal, and holding the gain at a substantially constant level in response to a fast signal transition in the digital output signal.

Claims

1. An integrated photodiode and receiver circuit on a substrate, the integrated receiver circuit comprising:

a first diffused region in the substrate for receiving an input signal;

a first circuit input terminal coupled to the first diffused region;

a circuit output terminal;

an input amplifier interposed between the first circuit input and receiver output terminals, the input amplifier being configured to receive and amplify the input signal to produce an amplified input signal, and wherein the input amplifier is further configured to vary the gain of the input amplifier responsive to a gain control signal;

a bandpass filter interposed between the input amplifier and the circuit output terminal, the bandpass filter being configured to receive and bandpass filter the amplified input signal so as to produce a filtered input signal;

a comparator interposed between the bandpass filter and the circuit output terminal, the comparator being configured to compare the filtered input signal to a detection threshold voltage level in order to generate a ditigal output signal;

a delay circuit interposed between the comparator and the circuit output terminal, the delay circuit being configured to receive the digital output signal and generate a delayed digital output signal responsive thereto;

an automatic gain control circuit configured to receive the filtered input signal, the automatic gain control circuit comparing the filtered input signal to an automatic gain control threshold voltage and generating the gain control signal responsive thereto;

an isolation control signal generator configured to receive the delayed digital output signal and generating an isolation control signal responsive thereto;

an isolation switch interposed between the input amplifier and the automatic gain control circuit, the isolation switch being configured to receive the isolation control signal, and, responsive thereto, isolate the automatic gain control circuit from the amplified input signal;

a second diffused region in the substrate;

an opaque layer formed over the second diffused region and spaced apart from the first diffused region such that the second diffused region is configured to receive a noise signal, and wherein the second diffused region is coupled to a second circuit input terminal; and

wherein the input amplifier is further configured to receive the noise signal received by the second diffused region and differentially amplify the input signal and noise signal to produce the amplified input signal.

2. The integrated receiver circuit of claim 1 wherein the isolation switch is further configured to isolate the comparator from the amplified input signal responsive to the isolation control signal.

3. The integrated receiver circuit of claim 1 wherein the isolation switch is further configured to isolate the bandpass filter from the amplified input signal responsive to the isolation control signal.

4. The integrated receiver circuit of claim 1 wherein the isolation control signal generator comprises a one-shot circuit configured to generate an output pulse of a predetermined duration responsive to a falling edge in the delayed digital output signal.

5. The integrated receiver of claim 1 wherein the isolation control signal generator comprises an edge triggered one-shot circuit configured to generate an output pulse of a predetermined duration responsive to each edge in the delayed digital output signal.

6. The integrated receiver of claim 5 wherein the edge triggered one-shot circuit comprises:

a first exclusive-OR gate having first and second input terminals and an output terminal, wherein the first input terminal is configured to receive the delayed digital output signal;

a resistor having first and second terminals, wherein the first terminal is configured to receive the delayed digital output signal, and further wherein the second terminal is coupled to the second input terminal of the first exclusive-OR gate; and

a capacitor coupled between the second input terminal of the first exclusive-OR gate and ground;

whereby the first exclusive-OR gate generates the isolation control signal at its output terminal responsive to the delayed digital output signal.

7. The integrated receiver of claim 5 wherein the isolation control signal generator further includes:

a feedback detect comparator configured to receive the amplified input signal and compare it to the detection threshold voltage level to produce a feedback detect signal;

a second exclusive-OR gate having first and second input terminals and an output terminal, wherein the first input terminal is configured to receive the feedback detect signal and the second input terminal is configured to receive the delayed digital output signal; and

an AND gate having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the output terminal of the first exclusive-OR gate and the second input terminal is coupled to the output terminal of the second exclusive-OR gate whereby the AND gate generates the isolation control signal at its output terminal.

8. A method for suppressing feedback in a photodiode and a receiver fabricated on a substrate, the method comprising the steps:

receiving an input signal with the photodiode;

amplifying the input signal to produce an amplified input signal;

controlling the gain of the input signal amplification responsive to the magnitude of the amplified input signal;

comparing the amplified input signal to a detection threshold voltage to produce a digital output signal;

holding the gain at a substantially constant level in response to a fast signal transition in the digital output signal;

providing a second photodiode;

shielding the second photodiode from the input signal such that the second photodiode receives a noise signal; and

wherein the step of amplifying the input signal to produce an amplified input signal includes differentially amplifying the input signal and the noise signal to produce the amplified input signal.

9. The method of claim 8 including the step of filtering the amplified input signal to produce a filtered input signal.

10. The method of claim 8 wherein:

the step of controlling the gain of the input signal amplification responsive to the magnitude of the ampified input signal includes the step of controlling the gain using an automatic gain control circuit; and

the step of holding the gain at a substantially constant level includes the steps;

generating an isolation signal responsive to the digital output signal, and

isolating the automatic gain control circuit from the amplified input signal responsive to the isolation signal.

11. The method of claim 10 wherein the step of comparing the amplified input signal to a detection threshold voltage includes using a comparator circuit to compare the amplified input signal to the detection threshold voltage and further including the step of isolating the comparator from the amplified input signal responsive to the isolation signal.

12. The method of claim 10 including:

filtering the amplified input signal using a bandpass filter to produce a filtered input signal; and

isolating the bandpass filter from the amplified input data signal responsive to the isolation signal.

13. The method of claim 10 wherein the step of generating an isolation signal includes generating a pulse of a predetermined duration responsive to each falling edge in the digital output signal.

14. The method of claim 10 wherein the step of generating an isolation signal includes generating a pulse of a predetermined duration responsive to each edge in the digital output signal.

15. The method of claim 8 wherein the step of comparing the filtered input signal to a detection threshold voltage to produce a digital output signal includes the step of introducing a time delay to the digital output signal.