VDD modulated SRAM for highly scaled, high performance cache

• US 6,556,471 B2
• Filed: 06/27/2001
• Issued: 04/29/2003
• Est. Priority Date: 06/27/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chappell, Barbara A., Young, Ian
• Primary Examiner(s): Lam, David
• Application Number:
  US09/893,236
• Publication Number:
  US 20030012048A1
• Time in Patent Office: 671 Days
• Field of Search: 365/154, 365/156, 365/205, 365/189.11, 365/189.05, 365/230.06, 365/203, 365/189.01
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a latch device in the SRAM cell relative to a conductance of an access device in the SRAM cell. By virtue of the increased relative conductance between the latch and access devices (beta ratio), the access device may be assume a wider width without jeopardizing the read stability of the cell.

Claims

1. An SRAM (“

Static Random Access Memory”

) cell comprising;

a latch device for storing a state of the SRAM cell;

an access device for performing a read and write operation;

a boost voltage source, wherein the boost voltage source is applied to the latch device, the boost voltage increasing a conductance of the latch device relative to a conductance of the access device.

2. The SRAM cell according to claim 1, wherein the latch device comprises a first inverter and a second inverter, the first inverter and second inverter configured in a cross-coupled arrangement.

3. The SRAM cell according to claim 2, wherein the each of the first inverter and second inverter includes a respective pull-up device and a pull-down device, the pull-up device operating to pull up a voltage at an output of a respective inverter and the pull-down device operating to pull down a voltage at an output of a respective inverter.

4. The SRAM cell according to claim 3, wherein the respective pull-up devices of the inverters are P-MOS transistors fabricated within at least one N well.

5. An SRAM (“

Static Random Access Memory”

) cell comprising;

a latch device for storing a state of the SRAM cell, the latch device comprising a first inverter and a second inverter, the first inverter and the second inverter configured in a cross-coupled arrangement, wherein each of the first inverter and second inverter includes a respective pull-up device and a pull-down device, the pull-up device operating to pull up a voltage at an output of a respective inverter and the pull-down device operating to pull down a voltage at an output of a respective inverter;

an access device for performing a read and write operation;

a boost voltage source, wherein the boost voltage source is applied to the latch device, the boost voltage increasing a conductance of the latch device relative to a conductance of the access device, wherein the boost voltage source is applied to the pull-up devices of the first and second inverters prior to one of a read operation and a write operation.

6. The SRAM cell according to claim 5, wherein the boost voltage source is modulated to operate at a chip voltage and a boost voltage, the boost voltage being larger in magnitude than the chip voltage, and the boost voltage source operates provides the boost voltage prior to one of a read and write operation.

7. An SRAM (“

Static Random Access Memory”

) cell comprising;

a latch device for storing a state of the SRAM cell, the latch device comprising a first inverter and a second inverter, the first inverter and the second inverter configured in a cross-coupled arrangement, wherein each of the first inverter and second inverter includes a respective pull-up device and a pull-down device, the pull-up device operating to pull up a voltage at an output of a respective inverter and the pull-down device operating to pull down a voltage at an output of a respective inverter;

an access device for performing a read and write operation, wherein the respective pull-up devices of the inverters are P-MOS transistors fabricated within at least one N well;

a boost voltage source, wherein the boost voltage source is applied to the latch device, the boost voltage increasing a conductance of the latch device relative to a conductance of the access device, wherein a boost voltage is applied to the N well.

8. A method for performing fast reading and writing to an SRAM cell including a latch device and an access device comprising:

providing a boost voltage source, the boost voltage source increasing a conductance of the latch device in the SRAM cell relative to a conductance of the access device in the SRAM cell;

prior to one of a read operation and a write operation, applying the boost voltage source to a pull-up device in the latch device;

performing one of a read operation and a write operation on the SRAM cell.

9. The method according to claim 8, wherein the boost voltage source is modulated between a chip voltage and a boost voltage, the boost voltage being greater in magnitude than the chip voltage.

10. The method according to claim 8, wherein performing one of a read operation and a write operation further includes:

precharging a bitline pair associated with the SRAM cell;

associating a wordline associated with the SRAM cell.

11. An SRAM array comprising:

at least one SRAM cell arranged in an array configuration, each SRAM cell comprising;

a latch device for storing a state of the SRAM cell;

an access device for performing a read and write operation;

a plurality of wordlines, each wordline controlling at least one access device;

a plurality of bitline pairs, wherein each bitline pair is coupled to at least one SRAM cell through an access device;

a boost voltage source, wherein the boost voltage source is applied to at least one latch device, the boost voltage increasing a conductance of the at least one latch device relative to a conductance of the at least one respective access device.

12. The SRAM array according to claim 11, wherein the boost voltage source is modulated between a first voltage and a boost voltage.

13. An SRAM array comprising:

at least one SRAM cell arranged in an array configuration, each SRAM cell comprising;

a latch device for storing a state of the SRAM cell;

an access device for performing a read and write operation;

a plurality of wordlines, each wordline controlling at least one access device;

a plurality of bitline pairs, wherein each bitline pair is coupled to at least one SRAM cell through an access device;

a boost voltage source, wherein the boost voltage source is applied to at least one latch device, the boost voltage increasing a conductance of the at least one latch device relative to a conductance of at least one respective access device, and wherein the boost voltage source is modulated between a first voltage and a boost voltage;

decoding logic for generating a control signal to control the boost voltage source.

14. A method for writing to an SRAM cell comprising:

(a) precharging a bitline pair associated with the cell;

(b) modulating a voltage applied to a latch device of the cell;

(c) applying a signal to cause a write operation.

15. The method according to claim 14, wherein the voltage is modulated by reducing it from a previous value.