Static RAM with optimized timing of driving control signal for sense amplifier
First Claim
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1. A static RAM comprising:
- a memory cell array having memory cells located at intersections of word lines and bit lines;
a sense amplifier for amplifying a voltage of said bit lines;
dummy memory cells selected when said word line is selected;
a dummy bit line connected to the dummy memory cells;
a timing signal generating circuit for generating a timing control signal in response to a change in potential of said dummy bit line; and
a dummy memory cell selecting circuit for inputting a word line group including a plurality of said word lines and selecting said dummy memory cell shared by the word line group in response to a selection of at least one of the word lines in said word line group.
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Abstract
The present invention is a static RAM comprising a memory cell array having memory cells located at intersections of word lines and bit lines, and a sense amplifier for amplifying a voltage of the bit lines; this static RAM further comprising: dummy memory cells selected when the word line is selected; a dummy bit line connected to the dummy memory cells; a timing signal generating circuit for generating a timing control signal in response to a change in potential of the dummy bit line; and a dummy memory cell selecting circuit for, in response to a selection of a word line in a word line group including a plurality of the word lines, selecting the dummy memory cell shared by the word line group.
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Citations
15 Claims
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1. A static RAM comprising:
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a memory cell array having memory cells located at intersections of word lines and bit lines;
a sense amplifier for amplifying a voltage of said bit lines;
dummy memory cells selected when said word line is selected;
a dummy bit line connected to the dummy memory cells;
a timing signal generating circuit for generating a timing control signal in response to a change in potential of said dummy bit line; and
a dummy memory cell selecting circuit for inputting a word line group including a plurality of said word lines and selecting said dummy memory cell shared by the word line group in response to a selection of at least one of the word lines in said word line group. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
a switch group for propagating or not propagating a dummy memory cell selecting signal output by said dummy memory cell selecting circuit to said dummy memory cells; and
a switch setting circuit for placing part or all of said switch group in a propagating state.
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11. A static RAM comprising:
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a memory cell array having memory cells located at intersections of word lines and bit lines;
a sense amplifier for amplifying a voltage of said bit lines in response to a sense amplifier enable signal;
a plurality of dummy memory cells aligned with said memory cell array and disposed in the direction of the bit lines;
a dummy bit line connected in parallel to the plurality of dummy memory cells;
a timing signal generating circuit for generating said sense amplifier enable signal in response to a change in potential of said dummy bit line; and
a dummy memory cell selecting circuit for selecting a plurality of the dummy memory cells in response to the selection of said word line. - View Dependent Claims (12, 13, 14, 15)
said dummy cell unit is provided for each of said word line groups; and
said dummy cell unit is selected by said dummy memory cell selecting circuit.
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15. The static RAM, according to claim 11, wherein each of said dummy memory cells comprises a latch circuit having two cross-connected inverters, and one of a pair of nodes in the latch circuits are connected to a high level or low level power source.
Specification