Non-volatile memory data protection

• US 6,556,476 B1
• Filed: 03/11/2002
• Issued: 04/29/2003
• Est. Priority Date: 03/11/2002
• Status: Expired due to Fees

• Current Assignee: Unigen Corporation
• Original Assignee: Unigen Corporation
• Inventors: Na, Hanjoo
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/094,756
• Time in Patent Office: 414 Days
• Field of Search: 365/185.04, 365/195, 365/189.07, 365/185.09, 365/185.11, 365/185.12
• US Class Current: 365/185.04
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A write-protected memory device has two write modes. Such memory device has many memory cells organized into pages. A normal write mode checks a one-bit flag collocated with every memory cell to see if writes are allowed. If the flag indicates a write operation to that memory cell is allowed, the flag is toggled and the cell is written. If the flag has previously been toggled, the write operation is prevented. A special write mode allows write operations to memory cells regardless of the state of the one-bit flag. The special write mode can be discerned in hardware by the loading of a register with a reprogrammable password, or the splitting of a normal single write-enable pin into two independent pins, e.g., normal write and special write. The memory operations can proceed either in page mode or cell-by-cell

Claims

1. A write-protected memory, comprising:

an addressable memory array including a plurality of memory cells;

a plurality of toggle flags each associated with each one of said memory cells;

a special-write input for controlling a direct writing of data to each of said memory cells; and

a normal-write input for conditionally writing data to each of said memory cells dependent on a pristine state of a corresponding one of the plurality of toggle flags;

wherein, data is prevented from being written into any of said plurality of memory cells by the normal-write input if said corresponding one of the plurality of toggle flags is not in a pristine state.

2. The memory of claim 1, wherein data is always allowed to written into any of said plurality of memory cells by the special-write input regardless of the state condition of any one of said corresponding plurality of toggle flags.

3. The memory of claim 1, wherein when data is allowed to be written into any of said plurality of memory cells with the normal-write input, the state condition of said corresponding one of said plurality of toggle flags is toggled.

4. The memory of claim 1, wherein when data has been allowed to be written into any of said plurality of memory cells with the normal-write input, the state condition of said corresponding one of said plurality of toggle flags is toggled to prevent future such normal-write operations.

5. The memory of claim 1, wherein data is written in pages into a corresponding page of said plurality of memory cells by the special-write input regardless of the state condition of any one of said corresponding plurality of toggle flags in that page.

6. The memory of claim 1, wherein data is written in pages into a corresponding page of said plurality of memory cells by the normal-write input only when the state condition of all of said corresponding plurality of toggle flags in that page are in their pristine condition.

7. The memory of claim 1, wherein:

the special-write input is software accessible only, and requires the use of a special access codeword or password for writing said plurality of memory cells if said corresponding one of the plurality of toggle flags is not in said pristine state;

wherein, said special access codeword or password can be re-written so only a unique user can thereafter access a special write operation.