Non-volatile static memory cell
First Claim
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1. A non-volatile SRAM cell, comprising:
- a nonvolatile memory element;
a volatile memory element coupled to said nonvolatile memory element;
a gate circuit coupled to said nonvolatile memory element, wherein said gate circuit (i) is configured to transfer data to and from a first input/output line into said volatile memory element and (ii) comprises (a) a first transistor coupled between said first input/output line and said non-volatile memory element and (b) a second transistor coupled between said first input/output line and said volatile memory element.
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Abstract
A non-volatile SRAM cell including (i) a nonvolatile memory element, (ii) a volatile memory element coupled to the nonvolatile memory element and (iii) a gate circuit coupled to the nonvolatile memory element. The gate circuit is configured to transfer data to and from a first input/output line into the volatile memory element.
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Citations
17 Claims
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1. A non-volatile SRAM cell, comprising:
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a nonvolatile memory element;
a volatile memory element coupled to said nonvolatile memory element;
a gate circuit coupled to said nonvolatile memory element, wherein said gate circuit (i) is configured to transfer data to and from a first input/output line into said volatile memory element and (ii) comprises (a) a first transistor coupled between said first input/output line and said non-volatile memory element and (b) a second transistor coupled between said first input/output line and said volatile memory element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A circuit comprising:
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volatile means for storing data;
non-volatile means for storing said data upon a power fail event, coupled to said volatile data storing means; and
means for recalling said data from said non-volatile data storing means into said volatile data storing means when power is reapplied to a device containing the circuit, wherein said recalling means comprises (a) a first transistor coupled between a first input/output line and said non-volatile means and (b) a second transistor coupled between said first input/output line and said volatile means.
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14. A method for recalling data previously stored in a volatile memory, comprising the sequential steps of:
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storing said data in a non-volatile memory element coupled to said volatile memory upon a power fail event; and
recalling said data from said non-volatile memory element into said volatile memory in response to an application of power to a device containing both the non-volatile memory element and the volatile memory, wherein said non-volatile memory comprises (a) a first transistor coupled between a first input/output line and said non-volatile memory element and (b) a second transistor coupled between said first input/output line and said volatile memory. - View Dependent Claims (15)
writing a predetermined digital logic value into said volatile memory, and reading said non-volatile memory element.
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16. A circuit comprising:
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a memory storage element;
a true bitline and a complement bitline configured to write data to and read data from said memory storage element; and
a floating gate device (i) coupled between said true bitline and said memory storage element and (ii) configured to store data from said memory storage element during a power down condition. - View Dependent Claims (17)
a second floating gate device (i) coupled between said complement bitline and said memory storage element and (ii) configured to store data from said memory storage element during said power down condition.
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Specification