Digital PLL circuit and signal regeneration method

• US 6,556,640 B1
• Filed: 12/04/1998
• Issued: 04/29/2003
• Est. Priority Date: 12/04/1997
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Baba, Mitsuo
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Ha, Dac V.
• Application Number:
  US09/205,878
• Time in Patent Office: 1,607 Days
• Field of Search: 375/215, 375/226, 375/360, 375/371, 375/373, 375/375, 375/376, 327/144, 327/150, 327/151, 327/152, 327/153, 327/154, 327/159, 327/161, 370/516-518
• US Class Current: 375/376
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

An input data signal is digitally sampled by a data sampling section using an N-phase clock signal including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained. An edge point detection operation section detects edge points in the N sample data signals in one cycle of an extracted clock signal and outputs an edge point operation output signal. A clock signal extraction section selects a clock signal from the N-phase clock signal based on the information of the edge point operation output signal and outputs the selected clock signal as the extracted clock signal. A delay section delays the N sample data signals of the parallel sample data signal and thereby outputs a parallel delayed sample data signal including N delayed sample data signals. A data regeneration section selects a delayed sample data signal from the N delayed sample data signals based on the information of the edge point operation output signal and outputs the selected delayed sample data signal as a regenerated data signal. Due to the delay by the delay section, extraction time of the digital PLL circuit can be decreased to 0 without enlarging the overhead in the input data signal.

Claims

1. A digital PLL circuit comprising:

a data sampling means which is supplied with an input data signal and an N-phase clock signal (N;

integer larger than

     1) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, for digitally sampling the input data signal using the N clock signals and thereby outputting a parallel sample data signal including N sample data signals;

an edge point detection operation means for acquiring the N sample data signals of the parallel sample data signal, detecting edge points in the acquired N sample data signals in one cycle of an extracted clock signal, and outputting an edge point operation output signal which includes information on the edge points in one cycle of the extracted clock signal;

a clock signal extraction means which is supplied with the N-phase clock signal and the edge point operation output signal outputted by the edge point detection operation means, for selecting a clock signal from the N clock signals of the N-phase clock signal based on the information of the edge point operation output signal and outputting the selected clock signal as the extracted clock signal;

a delay means for delaying the N sample data signals of the parallel sample data signal supplied from the data sampling means and thereby outputting a parallel delayed sample data signal including N delayed sample data signals; and

a data regeneration means which is supplied with the parallel delayed sample data signal outputted by the delay means and the edge point operation output signal outputted by the edge point detection operation means, for selecting a delayed sample data signal from the N delayed sample data signals of the parallel delayed sample data signal based on the information of the edge point operation output signal and outputting the selected delayed sample data signal as a regenerated data signal.

2. A digital PLL circuit as claimed in claim 1, wherein the extracted clock signal extracted by the clock signal extraction means is outputted to the outside of the digital PLL circuit.

3. A digital PLL circuit as claimed in claim 1, wherein the delay time of the delay means is set so that time necessary for obtaining the extracted clock signal based on a parallel sample data signal will not become longer than time necessary for obtaining the regenerated data signal from the parallel sample data signal.

4. A digital PLL circuit as claimed in claim 1, wherein the delay means delays the N sample data signals of the parallel sample data signal keeping phase differences between the N sample data signals.

5. A digital PLL circuit as claimed in claim 1, wherein the delay means includes N flip-flop lines each of which including M stages of flip-flops (M:

natural number), and each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by M bits.

6. A digital PLL circuit as claimed in claim 1, wherein the delay means includes a 1/L frequency demultiplier for demultiplying the frequencies of the N clock signals of the N-phase clock signal by L (L:

integer larger than

     1) and N flip-flop lines each of which including M stages of flip-flops (M;

natural number), and each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal whose frequency has been demultiplied by the 1/L frequency demultiplier to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by M×

L bits.

7. A digital PLL circuit as claimed in claim 1, wherein the edge point operation output signal outputted by the edge point detection operation means includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a rising edge of the input data signal.

8. A digital PLL circuit as claimed in claim 7, wherein the edge point operation output signal outputted by the edge point detection operation means includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.

9. A digital PLL circuit as claimed in claim 7, wherein the edge point operation output signal outputted by the edge point detection operation means includes information on the average of the phase numbers that indicate the rising edges of the input data signal in a predetermined period.

10. A digital PLL circuit as claimed in claim 1, wherein the edge point operation output signal outputted by the edge point detection operation means includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a falling edge of the input data signal.

11. A digital PLL circuit as claimed in claim 10, wherein the edge point operation output signal outputted by the edge point detection operation means includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.

12. A digital PLL circuit as claimed in claim 10, wherein the edge point operation output signal outputted by the edge point detection operation means includes information on the average of the phase numbers that indicate the falling edges of the input data signal in a predetermined period.

13. A digital PLL circuit as claimed in claim 12, wherein the clock signal extraction means utilizes the information on the average of the phase numbers that indicate the falling edges of the input data signal for the selection of the extracted clock signal.

14. A digital PLL circuit as claimed in claim 1, wherein the edge point detection operation means acquires the N sample data signals of the parallel sample data signal with timing in sync with the extracted clock signal.

15. A digital PLL circuit as claimed in claim 9, wherein the clock signal extraction means utilizes the information on the average of the phase numbers that indicate the rising edges of the input data signal for the selection of the extracted clock signal.

16. A digital PLL circuit as claimed in claim 1, wherein the data regeneration means is supplied with the extracted clock signal outputted by the clock signal extraction means, and outputs the regenerated data signal with timing in sync with the extracted clock signal.

17. A signal regeneration method comprising the steps of:

a data sampling step in which an input data signal is digitally sampled using an N-phase clock signal (N;

integer larger than

     1) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained;

an edge point detection operation step in which the N sample data signals of the parallel sample data signal are acquired, edge points in the acquired N sample data signals in one cycle of an extracted clock signal are detected, and an edge point operation output signal which includes information on the edge points in one cycle of the extracted clock signal is generated;

a clock signal extraction step in which the extracted clock signal is selected from the N clock signals of the N-phase clock signal based on the information of the edge point operation output signal;

a delay step in which the N sample data signals of the parallel sample data signal are delayed and thereby a parallel delayed sample data signal including N delayed sample data signals are obtained; and

a data regeneration step in which a delayed sample data signal is selected from the N delayed sample data signals of the parallel delayed sample data signal based on the information of the edge point operation output signal and the selected delayed sample data signal is outputted as a regenerated data signal.

18. A signal regeneration method as claimed in claim 17, wherein the extracted clock signal is outputted to the outside of the device that employs the signal regeneration method.

19. A signal regeneration method as claimed in claim 17, wherein the delay time of the delay step is set so that time necessary for obtaining the extracted clock signal based on a parallel sample data signal will not become longer than time necessary for obtaining the regenerated data signal from the parallel sample data signal.

20. A signal regeneration method as claimed in claim 17, wherein in the delay step, the N sample data signals of the parallel sample data signal are delayed keeping phase differences between the N sample data signals.

21. A signal regeneration method as claimed in claim 17, wherein the delay step is executed by a delay means which includes N flip-flop lines each of which including M stages of flip-flops (M:

natural number), in which each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by M bits.

22. A signal regeneration method as claimed in claim 17, wherein the delay step is executed by a delay means which includes a 1/L frequency demultiplier for demultiplying the frequencies of the N clock signals of the N-phase clock signal by L (L:

integer larger than

     1) and N flip-flop lines each of which including M stages of flip-flops (M;

natural number), in which each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal whose frequency has been demultiplied by the 1/L frequency demultiplier to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by M×

L bits.

23. A signal regeneration method as claimed in claim 17, wherein the edge point operation output signal generated in the edge point detection operation step includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a rising edge of the input data signal.

24. A signal regeneration method as claimed in claim 23, wherein the edge point operation output signal generated in the edge point detection operation step includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.

25. A signal regeneration method as claimed in claim 23, wherein the edge point operation output signal generated in the edge point detection operation step includes information on the average of the phase numbers that indicate the rising edges of the input data signal in a predetermined period.

26. A signal regeneration method as claimed in claim 17, wherein the edge point operation output signal generated in the edge point detection operation step includes information on the phase number of a clock signal in the N clock signal of the N-phase clock signal that indicates a falling edge of the input data signal.

27. A signal regeneration method as claimed in claim 26, wherein the edge point operation output signal generated in the edge point detection operation step includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.

28. A signal regeneration method as claimed in claim 26, wherein the edge point operation output signal generated in the edge point detection operation step includes information on the average of the phase numbers that indicate the falling edges of the input data signal in a predetermined period.

29. A signal regeneration method as claimed in claim 28, wherein in the clock signal extraction step, the information on the average of the phase numbers that indicate the falling edges of the input data signal is utilized for the selection of the extracted clock signal.

30. A signal regeneration method as claimed in claim 17, wherein in the edge point detection operation step, the N sample data signals of the parallel sample data signal are acquired with timing in sync with the extracted clock signal.

31. A signal regeneration method as claimed in claim 25, wherein in the clock signal extraction step, the information on the average of the phase numbers that indicate the rising edges of the input data signal is utilized for the selection of the extracted clock signal.

32. A signal regeneration method as claimed in claim 17, wherein in the data regeneration step, the regenerated data signal is outputted with timing in sync with the extracted clock signal.