Semiconductor processing techniques

• US 6,556,949 B1
• Filed: 05/18/1999
• Issued: 04/29/2003
• Est. Priority Date: 05/18/1999
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Lyon, Richard C.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Tsai, Carol S W
• Application Number:
  US09/314,275
• Time in Patent Office: 1,442 Days
• Field of Search: 702/33-36, 702/40, 702/79, 702/81-84, 702/117, 702/118, 702/119, 702/120-123, 702/140, 702/172, 702/176-178, 702/179, 702/181, 702/182-185, 702/FOR.103, 702/FOR.104, 702/FOR-123, 702/FOR-131, 702/FOR.135, 702/FOR.136, 702/FOR.137, 702/FOR.139, 702/FOR.170, 702/FOR.171, 700/121, 438/14, 438/15, 438/16, 345/133, 345/134, 345/140, 345/113
• US Class Current: 702/182
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
• CPC Class Codes: Y02P 90/80 Management or planning

Abstract

The present invention provides a manufacturing environment (210) for a wafer fab, and an SPDA data environment (212) for acquiring processing parameters and metrology data of production runs. A computation environment (214) processes the SPDA data to prepare delta graphs (536, 540 and 542) of the present invention. These delta graphs are then analyzed in an analysis environment (216). An MES environment (218) evaluates the analysis and executes a process intervention if the results of the analysis indicate processing or product quality problems in the process run of the manufacturing environment (210). Additionally, the invention provides for SPDA delta graphs of SPC control charts as well as SPC techniques utilizing process control limits based on delta graphs to identify, analyze and trouble-shoot semiconductor processing problems, in order to improve equipment reliability and wafer yield. The present invention also provides a process (700) for computer integrated equipment time states including a service procedures module (755) linked to preventive maintenance time states (735 and 742) and to a repair time state (731).

Claims

1. A method of analyzing semiconductor processing data employing a computer, the method comprising:

a) preparing a first graph of first semiconductor processing data comprising data of a first processing variable versus second semiconductor processing data comprising data of a second processing variable;

b) preparing a second graph of third semiconductor processing data comprising data of the first processing variable versus fourth semiconductor processing data comprising data of the second processing variable;

c) on the first graph, selecting a measure M1 of the second processing variable;

d) on the second graph, determining the measure M1 of the second processing variable;

e) overlaying M1 of the first graph on M1 of the second graph, wherein the first and second graphs are synchronized;

f) on the first graph, selecting at least a second measure M2 of the second processing variable;

g) on the second graph, determining the second measure M2;

h) determining values of the first processing variable comprising (1) on the first graph (i) a first value V1, corresponding to measure M1 and (ii) a second value V2, corresponding to measure M2 and (2) on the second graph (i) a third value V3, corresponding to measure M1 and (ii) a fourth value V4, corresponding to measure M2;

i) subtracting (1) V3 from V1, thereby obtaining a fifth value V5 and (2) V4 from V2, thereby obtaining a sixth value V6; and

j) subtracting the second graph from the first graph by forming a graph through (1) a first data point comprising first data point coordinates M1 and V5 and (2) a second data point comprising second data point coordinates M2 and V6, thereby connecting the first coordinates to the second coordinates and forming a delta graph of the first and second graphs.

2. The method of claim 1 wherein the first and third data comprise data selected from the group consisting of semiconductor processing data, semiconductor processing parameters and semiconductor metrology data.

3. The method of claim 1 wherein the second processing variable comprises processing time.

4. The method of claim 1 wherein the first and third data comprise semiconductor processing control chart data.

5. The method of claim 1 wherein preparing a first graph comprises preparing a first graph of a first semiconductor processing tool which is operating a semiconductor process and wherein preparing a second graph comprises preparing a second graph of a second semiconductor processing tool which is operating the semiconductor process.

17. The method of claim 1 wherein the first processing variable is selected from the group consisting of chamber bias forward power, chamber pressure and chamber RF peak-to-peak voltage.

6. A computer implemented method of determining performance differences between semiconductor processing tools, the method comprising:

a) executing a semiconductor processing technique in a first tool;

b) acquiring first data of a semiconductor processing variable versus time of the processing technique executed in the first tool;

c) preparing a first graph including the first data versus time, by using a graph coordinate axis having a time scale;

d) executing the processing technique in a second tool;

e) acquiring second data of the processing variable versus time of the processing technique executed in the second tool;

f) preparing a second graph including second data versus time, by using the graph coordinate axis;

g) overlaying the first graph on the second graph such that the first and second graphs are synchronized with respect to the time scale;

h) on the time scale, selecting a first plurality of measures comprising time measures;

i) on the first graph, determining a second plurality of measures comprising measures of the processing variable corresponding to the first plurality;

j) on the second graph, determining a third plurality of measures comprising measures of the processing variable corresponding to the first plurality;

k) subtracting the second plurality from the third plurality, thereby forming a fourth plurality comprising subtraction measures corresponding to the first plurality;

l) determining a fifth plurality comprising graph coordinates including the fourth plurality and the first plurality, such that the fifth plurality corresponds to the first plurality; and

m) employing the fifth plurality for forming a delta graph of the first and second graphs.

18. The method of claim 6 wherein the first processing variable is selected from the group consisting of chamber bias forward power, chamber pressure and chamber RF peak-to-peak voltage.

7. A method of controlling a computer implemented semiconductor fabrication process, the method comprising:

a) executing the process;

b) generating semiconductor fabrication process data;

c) preparing a first graph of first data comprising data of a first semiconductor processing variable versus second data comprising data of a second semiconductor processing variable, by using a graph coordinate axis having scale for the second processing variable;

d) preparing a second graph of third data comprising data of the first processing variable versus fourth data comprising data of the second processing variable, by using the graph coordinate axis;

e) overlaying the first graph on the second graph such that the first and second graphs are synchronized with respect to the graph coordinate axis;

f) on the graph coordinate axis, selecting a first plurality of measures comprising measures of the second processing variable;

g) on the first graph, determining a second plurality of measures comprising measures of the first processing variable corresponding to the first plurality;

h) on the second graph, determining a third plurality of measures comprising measures of the first processing variable corresponding to the first plurality;

i) subtracting the second plurality from the third plurality, thereby forming a fourth plurality comprising subtraction measures corresponding to the first plurality;

j) determining a fifth plurality comprising graph coordinates including the fourth plurality and the first plurality, such that the fifth plurality corresponds to the first plurality;

k) employing the fifth plurality for forming a delta graph of the first and second graphs;

l) analyzing the delta graph, thereby obtaining analysis results;

m) comparing the analysis results with predetermined process criteria; and

n) adjusting the process if the results do not meet the criteria.

15. The method of claim 7, wherein the predetermined process criteria comprise the delta graph forming a substantially straight line approximately parallel to data axis of the second data of the delta graph.

8. An apparatus comprising an environment adapted for:

(1) acquiring first data comprising data of a first semiconductor processing variable versus second data comprising data of a second semiconductor processing variable, (2) acquiring third data of the first processing variable versus fourth data comprising data of the second processing variable, (3) plotting the first data versus the second data, by using a graph coordinate axis having a scale for the second processing variable, thereby forming a first graph, (4) plotting the third data versus the fourth data by using the graph coordinate axis, thereby forming a second graph and (5) overlaying the first graph on the second graph such that the first and second graphs are synchronized with respect to the graph coordinate axis, (6) on the graph coordinate axis, selecting a first plurality of measures comprising measures of the second processing variable, (7) on the first graph, determining a second plurality of measures comprising measures of the first processing variable corresponding to the first plurality, (8) on the second graph, determining a third plurality of measures comprising measures of the first processing variable corresponding to the first plurality, (9) subtracting the second plurality from the third plurality, thereby forming a fourth plurality comprising subtraction measures corresponding to the first plurality, (10) determining a fifth plurality comprising graph coordinates including the fourth plurality and the first plurality, such that the fifth plurality corresponds to the first plurality and (11) employing the fifth plurality for constructing a delta graph of the first and second graphs.

19. The apparatus of claim 8 wherein the first processing variable is selected from the group consisting of chamber bias forward power, chamber pressure and chamber RF peak-to-peak voltage.

20. The apparatus of claim 8 wherein the first and third data comprise data selected from the group consisting of semiconductor processing data, semiconductor processing parameters and semiconductor metrology data.

9. An apparatus for controlling a semiconductor fabrication process, the apparatus comprising:

a) a first environment adapted for;

(1) acquiring first data comprising data of a first semiconductor processing variable versus second data comprising data of a second semiconductor processing variable, (2) acquiring third data comprising data of the first processing variable versus fourth data comprising data of the second processing variable, (3) plotting the first data versus the second data, by using a graph coordinate axis having a scale for the second processing variable, thereby forming a first graph, (4) plotting the third data versus the fourth data by using the graph coordinate axis, thereby forming a second graph and (5) overlaying the first graph on the second graph such that the first and second graphs are synchronized with respect to the graph coordinate axis, (6) on the graph coordinate axis, selecting a first plurality of measures comprising measures of the second processing variable, (7) on the first graph, determining a second plurality of measures comprising measures of the first processing variable corresponding to the first plurality, (8) on the second graph, determining a third plurality of measures comprising measures of the first processing variable corresponding to the first plurality, (9) subtracting the second plurality from the third plurality, thereby forming a fourth plurality comprising subtraction measures corresponding to the first plurality, (10) determining a fifth plurality comprising graph coordinates including the fourth plurality and the first plurality, such that the fifth plurality corresponds to the first plurality and (11) employing the fifth plurality for constructing a delta graph of the first and second graphs;

b) a second environment adapted for analyzing the delta graph, thereby obtaining an analysis result; and

c) a third environment adapted for communicating the result to the process.

10. The apparatus of claim 9 additionally comprising a fourth environment adapted for:

(1) comparing the analysis result with predetermined process criteria, and (2) intervening in the process if the analysis result does not meet the process criteria.

11. The apparatus of claim 10 wherein intervening comprises automatically intervening.

16. The apparatus of claim 10, wherein the predetermined process criteria comprise the delta graph forming a substantially straight line approximately parallel to a data axis of the second data of the delta graph.

12. A memory including a digitally encoded data structure adapted for forming a delta graph from a first graph and a second graph, the structure comprising:

a) a first digital transducer output of an IC processing chamber including the first graph comprising a first processing variable versus a second processing variable;

b) a second digital transducer output of an IC processing chamber including the second graph comprising the first processing variable versus the second processing variable;

c) a first algorithm for overlaying the first graph on the second graph, such that the first and second graphs are synchronized; and

d) a second algorithm for forming the delta graph from the synchronized first and second graphs, by subtracting the first digital transducer output comprising the first graph from the second digital transducer output comprising the second graph.

13. A method for enabling an equipment time state of an apparatus for executing a process wherein the process is integrated with the equipment time state, the method comprising:

a) defining equipment time states having a plurality of computer integrated time states including one or more time states which are integrated with the process;

b) determining a process control limit comprising a delta graph technique control limit; and

c) activating the one or more process integrated time states if the process is executed outside of the control limit.

14. An apparatus which is adapted for executing a process, the apparatus comprising:

a) computer integrated equipment time states;

b) a process control limit which is determined through a delta graph technique; and

c) a link between the delta graph technique and at least one of the time states wherein the link is activated if the process is executed outside the control limit.

21. A method of analyzing semiconductor processing data employing a computer, the method comprising:

a) preparing a first graph of first semiconductor processing data comprising data of a first processing variable versus second semiconductor processing data comprising data of a second processing variable, wherein the first variable is selected from the group consisting of chamber bias forward power, chamber pressure and chamber RF peak-to-peak voltage;

b) preparing a second graph of third semiconductor processing data comprising data of the first processing variable versus fourth semiconductor processing data comprising data of the second processing variable;

c) overlaying the first graph on the second graph, such that the first and second graphs are synchronized; and

d) forming a delta graph of the first and second graphs.

22. A method of analyzing data employing a computer, the method comprising:

a) preparing a first graph of first data comprising data of a first variable versus second data comprising data of a second variable;

b) preparing a second graph of third data comprising data of the first variable versus fourth data comprising data of the second variable;

c) overlaying the first graph on the second graph such that the first and second graphs are synchronized;

d) forming a delta graph of the first and second graphs; and

e) analyzing the delta graph to determine whether the delta graph forms a substantially straight line approximately parallel to a data axis of the second variable.