Apparatus and method to precisely position packets for a queue based memory controller

• US 6,557,057 B2
• Filed: 12/04/2001
• Issued: 04/29/2003
• Est. Priority Date: 12/29/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Swaminathan, Muthukumar P.
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US10/004,583
• Publication Number:
  US 20020073274A1
• Time in Patent Office: 511 Days
• Field of Search: 710/6, 710/39, 710/52, 710/54, 710/56, 710/58, 710/60, 713/400, 713/401, 713/502, 370/235, 370/412
• US Class Current: 710/54
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Claims

1. A method comprising:

assigning times for each queue position of a queue with a timestamp logic circuit, some of the queue positions having a packet scheduled at a scheduled time; and

adding bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet;

wherein the timestamp logic circuit comprises a plurality of chained timestamp logic units, the chained timestamp logic units including a plurality of standard timestamp logic units and a first timestamp logic unit, each standard timestamp logic unit corresponding to a queue position and each standard timestamp logic unit designating a scheduled time for the respective queue position, the first timestamp logic unit corresponding to the first queue position and designating the scheduled time for the first queue position.

2. The method of claim 1 further comprising storing each scheduled time for each queue position.

3. The method of claim 1 further comprising decrementing the scheduled time of the queue position creating an updated scheduling time.

4. The method of claim 3 further comprising storing the updated scheduling time.

5. The method of claim 4 further comprising transmitting the updated scheduling time to an adjacent queue position as the queue advances.

6. The method of claim 4 wherein the scheduled time is decremented by the clock frequency of a memory bus, which operates in conjunction with a memory controller responsible for scheduling the packet.

7. The method of claim 1 further comprising setting an updated scheduling time to a predetermined time when the queue is empty, the updated scheduling time being transmitted to an adjacent queue position as the queue advances.

8. The method of claim 1 further comprising:

if the queue stalls,

commanding packets to remain in the same queue position; and

continuing to decrement time.

9. The method of claim 1 further comprising subtracting a predetermined time value from all queue positions when a first queue position has more than a predetermined scheduled time.

10. The method of claim 9 wherein the predetermined time value subtracted from all queue positions is four when a first queue position has more than the predetermined scheduled time of three.