System and method for low-noise control of radio frequency devices

• US 6,557,062 B1
• Filed: 12/09/1999
• Issued: 04/29/2003
• Est. Priority Date: 12/09/1999
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Inc. (Northrop Grumman Corporation)
• Inventors: Shaler, Barton G., Caras, Steve
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/456,685
• Time in Patent Office: 1,237 Days
• Field of Search: 710/71, 710/110, 713/400, 713/500, 713/600, 370/278, 370/282, 370/296, 370/310, 370/507, 370/520
• US Class Current: 710/110
• CPC Class Codes: G08C 17/02 using a radio link

Abstract

A system and method for controlling Radio Frequency (RF) devices. A serial RF control bus (106) provides a half-duplex serial communication interconnect path between a bus master (108) and one or more bus slaves (110). The bus master is coupled to a processor (102), and each bus slave is coupled to an RF device (104) that operates without a free-running clock. The processor controls the RF devices by sending and receiving messages over the RF control bus. The bus master and bus slaves format these messages for transmission across the RF control bus. The RF control bus includes a bi-directional data line (120), a first clock line (124), and a second clock line (122). The first clock line is asserted by the bus master when transmitting serial data to and receiving serial data from the RF slaves via the data line. The second clock line is asserted by the RF slaves when transmitting serial data to the bus master via the data line.

Claims

1. A control bus for providing a communication interconnect path between a bus master and one or more bus slaves, wherein the bus master is coupled to a processor and each bus slave is coupled to a Radio Frequency (RF) device that operates without a free-running clock, the control bus comprising:

a bi-directional data line coupled to the bus master and to the one or more bus slaves;

a first clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the bus master when transmitting serial data to or receiving serial data from the one or more bus slaves via said bi-directional data line; and

a second clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the one or more bus slaves when transmitting serial data to the bus master via said bi-directional data line.

2. The control bus of claim 1, wherein said bi-directional data line, said first clock line, and said second clock line are Low Voltage Differential Signal (LVDS) paths.

3. A control bus for providing a communication interconnect path between a bus master and one or more bus slaves, wherein the bus master is coupled to a processor and each bus slave is coupled to an RF device that operates without a free-running clock, the control bus comprising:

a first data line coupled to the bus master and to the one or more bus slaves;

a second data line coupled to the bus master and to the one or more bus slaves;

a first clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the bus master when transmitting serial data to the one or more bus slaves via said first data line or receiving serial data from the one or more bus slaves via said second data line; and

a second clock line, coupled to the bus master and to the one or more bus slaves, to be asserted by the one or more bus slaves when transmitting serial data to the bus master via said second data line.

4. The control bus of claim 3, wherein said first data line, said second data line, said first clock line, and said second clock line are LVDS paths.

5. A system for RF control, comprising:

a processor;

a bus master coupled to said processor;

a bus slave;

an RF device coupled to said bus slave; and

an RF control bus, including;

a bi-directional data line coupled to said bus master and to said bus slave,

a first clock line, coupled to said bus master and to said bus slave, to be asserted by said bus master when transmitting serial data to or receiving serial data from said bus slave via said bi-directional data line, and

a second clock line, coupled to said bus master and to said bus slave, to be asserted by said bus slave when transmitting serial data to said bus master via said bi-directional data line.

6. The system of claim 5, further comprising:

a first First-In/First-Out (FIFO) device, wherein said processor loads a parallel transmit message into said first FIFO device and said bus master retrieves said parallel transmit message;

a second FIFO device, wherein said bus master loads a parallel receive message into said second FIFO device and said processor retrieves said parallel receive message; and

a status line coupled between said bus master and said processor.

7. The system of claim 5, wherein said processor sends a parallel transmit message to said bus master, and wherein said bus master converts said parallel transmit message to a serial message format and transmits said message to said bus slave via said RF control bus.

8. The system of claim 7, wherein said bus master transmits a synchronization burst to said bus slave via said data line before transmitting said message to said bus slave.

9. The system of claim 7, wherein said serial message format includes a standard message format and a variable length message format.

10. The system of claim 7, wherein said transmitted message includes a resource address and a command, said bus slave includes a physical address, and wherein said bus slave determines whether said resource address matches said physical address, and if so, responds by sending a slave response message to said bus master and executes said command.

11. The system of claim 10, wherein said command comprises a write command and said slave response message comprises a status message.

12. The system of claim 7, wherein said transmitted message includes a resource address and a command, said bus slave includes a logical address, and wherein said bus slave determines whether said resource address matches said logical address, and if so, executes said command.

13. The system of claim 5, further comprising:

a first driver coupled between said bus master and said bi-directional data line;

a first receiver coupled between said bus master and said bi-directional data line;

a second driver coupled between said bus master and said first clock line;

a second receiver coupled between said bus master and said second clock line;

a third driver coupled between said bus slave and said bi-directional data line;

a third receiver coupled between said bus slave and said bi-directional data line;

a fourth receiver coupled between said bus slave and said first clock line; and

a fourth driver coupled between said bus slave and said second clock line.

14. The system of claim 13, wherein said bi-directional data line, said first clock line, and said second clock line are differential signal paths, wherein said first, second, third, and fourth drivers are LVDS drivers, and wherein said first, second, third, and fourth receivers are LVDS receivers.

15. The system of claim 5, wherein said RF device operates without a free-running clock.

16. A method of controlling an RF device, wherein an RF control bus interconnects a bus master and a bus slave, wherein the bus slave is coupled to the RF device and the bus master is coupled to a processor, and wherein the RF control bus includes a data line, a first clock line, and a second clock line, comprising the steps of:

(a) sending a parallel transmit message from the processor to the bus master;

(b) converting the parallel transmit message into a serial data stream;

(c) formatting said serial data stream according to a serial message format, thereby creating a formatted message;

(d) sending a synchronization burst to the bus slave via the data line;

(e) asserting the first clock line while sending said formatted message from the bus master to the bus slave via the data line; and

(f) determining whether the bus slave is the intended recipient of said formatted message, and if so, formatting a status message and asserting the first and second clock lines while sending said status message from the bus slave to the bus master via the data line.

17. The method of claim 16, wherein the first and second clock lines are quiet during said synchronization burst.