CPU expandability bus

• US 6,557,065 B1
• Filed: 12/20/1999
• Issued: 04/29/2003
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Peleg, Alex D., Golbert, Adi
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US09/466,890
• Time in Patent Office: 1,226 Days
• Field of Search: 710/100, 710/300, 710/305, 710/306, 710/307, 710/308, 710/312, 710/313, 710/315
• US Class Current: 710/300
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function

Abstract

Embodiments of the present invention provide a computer system with a high speed, high bandwidth expandability bus for integrated and non-integrated CPU products. The computer system includes a processor, a chipset coupled to the processor, a graphics processor coupled to the chipset for controlling a video display and a main memory coupled to the chipset. The computer system further includes an expandability bus, which is coupled at one end to the chipset and at the other end to a replaceable electronic component. The expandability bus can be changeably configured to enable or disable bus mastering at both ends, as required, to operate with whichever replaceable electronic component is installed.

Claims

1. A computer system with a high speed, high bandwidth expandability bus comprising:

a processor;

a chipset coupled to said processor;

an expandability bus coupled at a first end to said chipset; and

an electronic component coupled to a second end of said expandability bus, said expandability bus being configurable to enable bus mastering at said first and second ends and said expandability bus being configured to operate with said electronic component;

said electronic component being replaceable and said expandability bus being changeably configurable to operate with a replacement electronic component.

2. The computer system of claim 1, wherein said electronic component is selected from the group comprising:

a co-processor;

a dynamic random access memory (DRAM);

a rambus DRAM (RDRAM); and

a graphics processor.

3. The computer system of claim 1, wherein said electronic component is replaced by said replacement electronic component and said expandability bus is reconfigured to operate with said replacement electronic component.

4. The computer system of claim 3, wherein the reconfiguration of said expandability bus is performed using a setup procedure specific to said computer system.

5. The computer system of claim 1, wherein said chipset comprises:

a northbridge chip coupled to said processor, wherein said northbridge chip includes the main system logic functions of said computer system; and

a southbridge chip coupled to said northbridge chip.

6. The computer system of claim 5, wherein said northbridge chip is coupled to said southbridge chip by a proprietary bus.

7. The computer system of claim 5, wherein said northbridge chip is further coupled to a graphics processor, said electronic component, and a main memory.

8. The computer system of claim 7, wherein said northbridge chip is coupled to said graphics processor using either an advanced graphics port bus or a second expandability bus.

9. The computer system of claim 7, wherein said northbridge chip is coupled to said main memory using either a main memory bus or a second expandability bus.

10. A computer system with a high speed, high bandwidth expandability bus comprising:

a processor means;

a chipset means coupled to said processor means;

an expandability bus means coupled at a first end to said chipset means; and

an electronic component means coupled to a second end of said expandability bus means, said expandability bus means being configurable to enable bus mastering at said first and second ends and said expandability bus means being configured to operate with said electronic component means;

said electronic component means being replaceable and said expandability bus means being changeably configurable to operate with a replacement electronic component means.

11. The computer system of claim 10, wherein said electronic component means is selected from the group comprising:

a co-processor means;

a dynamic random access memory (DRAM) means;

a rambus DRAM (RDRAM) means; and

a graphics processor means.

12. The computer system of claim 10, wherein said electronic component means is replaced by said replacement electronic component means and said expandability bus means is reconfigured to operate with said replacement electronic component means.

13. The computer system of claim 10, wherein the reconfiguration of said expandability bus means is performed using a setup procedure means specific to said computer system.

14. The computer system of claim 10, wherein said chipset comprises:

a northbridge chip means coupled to said processor means, wherein said northbridge chip means includes the main system logic functions of said computer system; and

a southbridge chip means coupled to said northbridge chip means.

15. The computer system of claim 14, wherein said northbridge chip means is coupled to said southbridge chip means by a proprietary bus means.

16. The computer system of claim 14, wherein said northbridge chip means is further coupled to a graphics processor means, said electronic component means, and a main memory means.

17. The computer system of claim 16, wherein said northbridge chip means is coupled to said graphics processor means using either an advanced graphics port bus means or a second expandability bus means.

18. The computer system of claim 16, wherein said northbridge chip means is coupled to said main memory means using either an advanced graphics port bus means or a second expandability bus means.

19. An integrated processor computer system with a high speed, high bandwidth expandability bus comprising:

an integrated processor;

a chipset coupled to said processor;

a first expandability bus coupled at a first end to said integrated processor;

an electronic component coupled at a second end to said expandability bus, said expandability bus being configurable to enable bus mastering at said first and second ends and said expandability bus being configured to operate with said electronic component, said electronic component being replaceable and said expandability bus being changeably configurable to operate with a replacement electronic component; and

a main memory coupled to said integrated processor using a second expandability bus.

20. The computer system of claim 19, wherein said integrated processor comprises:

a central processing unit (CPU);

a northbridge chip;

a cache random access memory (RAM); and

a graphics processor.

21. The computer system of claim 19, wherein said electronic component is selected from the group comprising:

a co-processor;

a dynamic random access memory (DRAM);

a rambus DRAM (RDRAM); and

a graphics processor.

22. The computer system of claim 19, wherein said electronic component is replaced by said replacement electronic component and said expandability bus is reconfigured to operate with said replacement electronic component.

23. The computer system of claim 22, wherein the reconfiguration of said expandability bus is performed using a setup procedure specific to said computer system.

24. The computer system of claim 19, wherein said chipset comprises:

a southbridge chip coupled to said integrated processor.

25. The computer system of claim 20, further comprising a second CPU coupled to said integrated processor using a third expandability bus.

26. The computer system of claim 25, wherein said third expandability bus is permanently configured to operate with said second CPU.

27. A multi-processor computing system with a high-speed, high-bandwidth expandability bus comprising:

a first processor;

a second processor coupled to said first processor;

a chipset coupled to at least one of said first and second processors;

a graphics processor coupled to one of said first processor, said second processor and said chipset for controlling a video display;

a main memory coupled to one of said first processor, said second processor and said chipset; and

an expandability bus coupled at a first end to one of said first processor, said second processor and said chipset; and

an electronic component coupled to a second end of said expandability bus, said expandability bus being configurable to enable bus mastering at said first and second ends and said expandability bus being configured to operate with said electronic component;

said electronic component being replaceable and said expandability bus being changeably configurable to operate with a replacement electronic component.