Method and apparatus for selectively compacting test responses

• US 6,557,129 B1
• Filed: 07/20/2000
• Issued: 04/29/2003
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US09/619,988
• Time in Patent Office: 1,013 Days
• Field of Search: 714/724, 714/726, 714/727, 714/728, 714/729, 714/30, 714/732, 714/733
• US Class Current: 714/729
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

Claims

1. An apparatus for selectively compacting test responses of an integrated circuit, comprising:

a plurality of scan chains within the integrated circuit to store test responses that indicate faults in the integrated circuit;

at least one spatial compactor to compress the test responses stored within the scan chains; and

a selector circuit coupled between the scan chains and the spatial compactor that masks one or more of the test responses received from the scan chains to the spatial compactor;

the spatial compactor including a feedback-free network of combinational logic.

2. The apparatus of claim 1, wherein the selector circuit includes a register that stores an identification of one of the scan chains and a flag, the flag when activated allows only the test response associated with a scan chain identified in the register to pass to the compactor and the flag when deactivated allows all of the test responses pass to the compactor, except for the test response identified in the register.

3. The apparatus of claim 1, wherein each scan chain has an output and the selector circuit includes a set of logic gates having first inputs coupled to the outputs of the scan chains, second inputs coupled to one or more control lines, and outputs coupled to the compactor, wherein with the one or more control lines activated the logic gates pass data on the outputs of the scan chains to the compactor and with the one or more control lines deactivated the logic gates prevent the data on the outputs of the scan chains from passing to the compactor.

4. The apparatus of claim 1 wherein each scan chain has an output and the selector circuit includes a set of logic gates having first inputs coupled to the outputs of the scan chains and second inputs coupled to a register, wherein data loaded into the register controls which scan chains are passed to the compactor.

5. The apparatus of claim 1 wherein the compactor and selector circuit are physically located on the integrated circuit.

6. The apparatus of claim 1 wherein the compactor and selector circuit are physically located externally of the integrated circuit.

7. The apparatus of claim 1 wherein masking a test response includes masking one or more bits of a test response in a scan chain.

8. The apparatus of claim 1 wherein masking a test response includes masking all bits in a scan chain that includes the test response.

9. The apparatus of claim 1, wherein the selector circuit masks test responses having unknown states.

10. The apparatus of claim 1, wherein the selector circuit is controlled by an external ATE.

11. The apparatus of claim 1, wherein the selector circuit includes a register and a decoder coupled to the register, the decoder being responsive to contents of the register for controlling whether the test response from the scan chains pass to the compactor.

12. The apparatus of claim 1, wherein the feedback-free network of combination logic includes Exclusive-OR gates, Exclusive-NOR gates or combinations thereof.

13. The apparatus of claim 12, wherein an output of the spatial compactor is observed in real time.

14. The apparatus of claim 1, wherein the feedback-free network is devoid of memory elements.

23. The method of claim 11 further including:

loading a plurality of scan chains located within the integrated circuit with test patterns;

storing the test responses in the scan chains;

loading a register with a scan chain identifier that uniquely identifies one of the scan chains; and

optionally configuring the selector circuit so that either all of the test responses in the scan chains are passed to the compactor except the test response stored in the scan chain identified in the register or only the test response stored in the scan chain identified in the register is passed to the compactor and all other test responses are masked from the compactor.

15. A method for selectively compacting test responses of an integrated circuit, comprising:

passing N test responses in an integrated circuit to a selector circuit;

using the selector circuit, selectively preventing between 0 and N of the test responses from being passed to a compactor while allowing the remaining test responses to be passed to the compactor; and

compacting the test responses passed to the compactor by the selector circuit;

wherein the selector circuit masks test responses with unknown states;

wherein the compacting is achieved using a spatial compactor having a feedback-free network of combination logic.

16. The method of claim 15 wherein passing the test responses to the selector circuit includes shifting each test response serially to the selector circuit.

17. The method of claim 15 further including:

loading scan chains located within the integrated circuit with predetermined test patterns for testing the integrated circuit; and

generating and storing test responses in response to applying the test patterns to the integrated circuit.

18. The method of claim 15 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

generating and storing test responses in the scan chains;

identifying one of the scan chains; and

wherein selectively preventing includes preventing only the test response in the identified scan chain from being passed to the compactor.

19. The method of claim 15 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

storing test responses in the scan chains;

identifying one scan chain as a scan chain of interest and passing only the test response within the identified scan chain to the compactor while preventing all other test responses from being passed to the compactor.

20. The method of claim 15 further including loading a scan chain identifier into a register, the scan chain identifier uniquely identifying one of the scan chains.

21. The method of claim 15 wherein selectively preventing the test responses from being passed to the compactor includes preventing one or more bits of a test response from being passed to the compactor while allowing other bits of the test response to pass to the compactor.

22. The method of claim 15 where selectively preventing the test responses from being passed to the compactor includes preventing all bits of a test response from being passed to the compactor.

24. The method of claim 15 wherein the selectively preventing includes allowing all of the test responses to pass to the compactor.

25. The method of claim 15, wherein the compactor is a spatial compactor.

26. The method of claim 15, further including controlling the selector circuit via an external ATE.

27. An apparatus for selectively compacting test responses of an integrated circuit, comprising:

means for storing a plurality of test responses that include information relating to faults within the integrated circuit;

selection means for selectively masking the test responses; and

means for spatially compacting the test responses selected by the selection means, the spatial compacting means including a feedback-free network;

wherein selection means for selectively masking includes decoding means for decoding contents of a scan chain identification register.

28. The apparatus of claim 27 wherein the selection means for selectively masking includes means for either allowing all of the test responses to pass to the means for compacting or for masking any variable number of test responses to prevent the masked test responses from being passed to the means for compacting.

29. The apparatus of claim 27 wherein the selection means for selectively masking includes means for selecting between the following modes of operation:

a) all test responses are compacted;

or

b) all test responses are compacted except one identified test response.

30. The apparatus of claim 27 wherein the selection means for selectively masking includes means for selecting between the following modes of operation:

a) all test responses are compacted;

or

b) only one identified test response is compacted.

31. The apparatus of claim 27 wherein the means for storing a plurality of test responses includes scan chain means for serially receiving predetermined test patterns, for applying the test patterns to the integrated circuit and for storing the test responses.

32. The apparatus of claim 27, wherein the selection means is controlled to mask test responses with unknown states.

33. The apparatus of claim 27, further including an external ATE to control the selection means.

34. An apparatus for selectively compacting test responses of an integrated circuit, comprising:

a plurality of scan chains within the integrated circuit to store test responses that indicate faults in the integrated circuit;

at least one spatial compactor to compress the test responses stored within the scan chains; and

a selector circuit coupled between the scan chains and the spatial compactor that masks one or more of the test responses from the spatial compactor,

wherein the selector circuit includes a register that stores an identification of one of the scan chains and a flag which when the flag is activated allows only the test response associated with a scan chain identified in the register to pass to the compactor and when the flag is deactivated allows all of the test responses pass to the compactor, except for the test response identified in the register.

35. The apparatus of claim 34, wherein each scan chain has an output and the selector circuit includes a set of logic gates having first inputs coupled to the outputs of the scan chains, second inputs coupled to one or more control lines, and outputs coupled to the compactor, wherein with the one or more control lines activated the logic gates pass data on the outputs of the scan chains to the compactor and with the one or more control lines deactivated the logic gates prevent the data on the outputs of the scan chains from passing to the compactor.

36. The apparatus of claim 34 wherein the compactor and selector circuit are physically located on the integrated circuit.

37. The apparatus of claim 34 wherein the compactor and selector circuit are physically located externally of the integrated circuit.

38. The apparatus of claim 34 wherein masking a test response includes masking one or more bits of a test response in a scan chain.

39. The apparatus of claim 34 wherein masking a test response includes masking all bits in a scan chain that includes the test response.

40. A method for selectively compacting test responses of an integrated circuit, comprising:

passing N test responses in an integrated circuit to a selector circuit;

using the selector circuit, selectively preventing between 0 and N of the test responses from being passed to a compactor while allowing the remaining test responses to be passed to the compactor; and

compacting the test responses passed to the compactor by the selector circuit using a spatial compactor that includes a feedback-free network of combinational logic,

wherein the selector circuit masks test responses with unknown states;

loading a scan chain identifier into a register, the scan chain identifier uniquely identifying one of the scan chains.

41. The method of claim 40 wherein passing the test responses to the selector circuit includes shifting each test response serially to the selector circuit.

42. The method of claim 40 further including:

loading scan chains located within the integrated circuit with predetermined test patterns for testing the integrated circuit; and

generating and storing test responses in response to applying the test patterns to the integrated circuit.

43. The method of claim 40 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

generating and storing test responses in the scan chains;

identifying one of the scan chains; and

wherein selectively preventing includes preventing only the test response in the identified scan chain from being passed to the compactor.

44. The method of claim 40 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

storing test responses in the scan chains;

identifying one scan chain as a scan chain of interest and passing only the test response within the identified scan chain to the compactor while preventing all other test responses from being passed to the compactor.

45. The method of claim 40 wherein selectively preventing the test responses from being passed to the compactor includes preventing one or more bits of a test response from being passed to the compactor while allowing other bits of the test response to pass to the compactor.

46. The method of claim 40 where selectively preventing the test responses from being passed to the compactor includes preventing all bits of a test response from being passed to the compactor.

47. The method of claim 40 further including:

loading a plurality of scan chains located within the integrated circuit with test patterns;

storing the test responses in the scan chains; and

optionally configuring the selector circuit so that either all of the test responses in the scan chains are passed to the compactor except the test response stored in the scan chain identified in the register or only the test response stored in the scan chain identified in the register is passed to the compactor and all other test responses are masked from the compactor.

48. The method of claim 40 wherein the selectively preventing includes allowing all of the test responses to pass to the compactor.

49. A method for selectively compacting test responses of an integrated circuit, comprising:

passing N test responses in an integrated circuit to a selector circuit;

using the selector circuit, selectively preventing between 0 and N of the test responses from being passed to a compactor while allowing the remaining test responses to be passed to the compactor; and

compacting the test responses passed to the compactor by the selector circuit;

controlling the selector circuit via an external ATE.

50. The method of claim 49 wherein passing the test responses to the selector circuit includes shifting each test response serially to the selector circuit.

51. The method of claim 49 further including:

loading scan chains located within the integrated circuit with predetermined test patterns for testing the integrated circuit; and

generating and storing test responses in response to applying the test patterns to the integrated circuit.

52. The method of claim 49 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

generating and storing test responses in the scan chains;

identifying one of the scan chains; and

wherein selectively preventing includes preventing only the test response in the identified scan chain from being passed to the compactor.

53. The method of claim 49 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

storing test responses in the scan chains;

identifying one scan chain as a scan chain of interest and passing only the test response within the identified scan chain to the compactor while preventing all other test responses from being passed to the compactor.

54. The method of claim 49 further including loading a scan chain identifier into a register, the scan chain identifier uniquely identifying one of the scan chains.

55. The method of claim 49 wherein selectively preventing the test responses from being passed to the compactor includes preventing one or more bits of a test response from being passed to the compactor while allowing other bits of the test response to pass to the compactor.

56. The method of claim 49 where selectively preventing the test responses from being passed to the compactor includes preventing all bits of a test response from being passed to the compactor.

57. The method of claim 49 further including:

loading a plurality of scan chains located within the integrated circuit with test patterns;

storing the test responses in the scan chains;

loading a register with a scan chain identifier that uniquely identifies one of the scan chains; and

optionally configuring the selector circuit so that either all of the test responses in the scan chains are passed to the compactor except the test response stored in the scan chain identified in the register or only the test response stored in the scan chain identified in the register is passed to the compactor and all other test responses are masked from the compactor.

58. The method of claim 49 wherein the selectively preventing includes allowing all of the test responses to pass to the compactor.

59. A method for selectively compacting test responses of an integrated circuit, comprising:

passing N test responses in an integrated circuit to a selector circuit;

using the selector circuit, selectively preventing between 0 and N of the test responses from being passed to a compactor while allowing the remaining test responses to be passed to the compactor; and

compacting the test responses passed to the compactor by the selector circuit using a spatial compactor having a feedback-free network of combinational logic;

wherein the selection means is controlled to mask test responses with unknown states.

60. The method of claim 59 wherein passing the test responses to the selector circuit includes shifting each test response serially to the selector circuit.

61. The method of claim 59 further including:

loading scan chains located within the integrated circuit with predetermined test patterns for testing the integrated circuit; and

generating and storing test responses in response to applying the test patterns to the integrated circuit.

62. The method of claim 59 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

generating and storing test responses in the scan chains;

identifying one of the scan chains; and

wherein selectively preventing includes preventing only the test response in the identified scan chain from being passed to the compactor.

63. The method of claim 59 further including:

loading scan chains located within the integrated circuit with predetermined test patterns;

storing test responses in the scan chains;

identifying one scan chain as a scan chain of interest and passing only the test response within the identified scan chain to the compactor while preventing all other test responses from being passed to the compactor.

64. The method of claim 59 further including loading a scan chain identifier into a register, the scan chain identifier uniquely identifying one of the scan chains.

65. The method of claim 59 wherein selectively preventing the test responses from being passed to the compactor includes preventing one or more bits of a test response from being passed to the compactor while allowing other bits of the test response to pass to the compactor.

66. The method of claim 59 where selectively preventing the test responses from being passed to the compactor includes preventing all bits of a test response from being passed to the compactor.

67. The method of claim 59 further including:

loading a plurality of scan chains located within the integrated circuit with test patterns;

storing the test responses in the scan chains;

loading a register with a scan chain identifier that uniquely identifies one of the scan chains; and

optionally configuring the selector circuit so that either all of the test responses in the scan chains are passed to the compactor except the test response stored in the scan chain identified in the register or only the test response stored in the scan chain identified in the register is passed to the compactor and all other test responses are masked from the compactor.

68. The method of claim 59 wherein the selectively preventing includes allowing all of the test responses to pass to the compactor.