Method of configuring FPGAS for dynamically reconfigurable computing

• US 6,557,156 B1
• Filed: 04/10/2000
• Issued: 04/29/2003
• Est. Priority Date: 08/28/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Guccione, Steven A.
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/546,460
• Time in Patent Office: 1,114 Days
• Field of Search: 716/1, 716/16, 716/17, 716/18
• US Class Current: 716/117
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method of configuring FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.

Claims

1. A method of generating configuration information for a field programmable gate array (FPGA), the FPGA being connected to a host processor for configuration thereby;

the method comprising;

programming the host processor with instructions in a programming language;

instantiating elements from a library of elements compatible with the programming language; and

generating executable code in response to the programmed instructions and the instantiated library elements, the executable code including compiled placement and routing information.

2. The method of claim 1, further comprising providing a compiler for the programming language to the host processor.

3. The method of claim 1, further comprising:

executing the executable code; and

configuring the FPGA from the host processor in response to executing the executable code.

4. The method of claim 1, wherein the FPGA is capable of dynamically reconfigurable computing.

5. The method of claim 4, further comprising reconfiguring at least a portion of the FPGA.

6. The method of claim 5, further wherein reconfiguring at least a portion of the FPGA is in response to executing the executable code.

7. The method of claim 5, wherein reconfiguring at least a portion of the FPGA occurs during operation of the FPGA.

8. The method of claim 1, wherein the programming language is a high level programming language.

9. The method of claim 8, wherein the high level programming language is part of a Java environment.

10. The method of claim 1, further comprising using the instantiated library elements to generate a parameterized cell.

11. The method of claim 10, wherein the parameterized cell is a counter parameterized by the number of bits in the counter.

12. A method of configuring a field programmable gate array (FPGA) for dynamically reconfigurable computing, the method comprising:

programming a host processor with instructions in a programming language;

generating executable code in response to the programmed instructions, the executable code including compiled placement and routing information; and

connecting the host processor to the FPGA for configuration of the FPGA by the host processor via the executable code.

13. The method of claim 12, wherein the programming language is a high level programming language.

14. The method of claim 13, wherein the high level programming language is part of a Java environment.

15. The method of claim 12, further comprising providing a compiler for the programming language to the host processor.

16. The method of claim 15, further comprising instantiating elements from a library of elements compatible with the compiler.

17. The method of claim 12, wherein the host processor comprises a compiler for the programming language, the method further comprising instantiating elements from a library of elements compatible with the compiler.

18. The method of claim 17, further comprising using the instantiated library elements to generate a parameterized cell.

19. The method of claim 18, wherein the parameterized cell is a counter parameterized by the number of bits in the counter.

20. The method of claim 12, further comprising:

executing the executable code; and

reconfiguring at least a portion of the FPGA in response to executing the executable code.

21. The method of claim 20, wherein reconfiguring at least a portion of the FPGA is accomplished via the host processor.

22. The method of claim 20, wherein reconfiguring at least a portion of the FPGA occurs during operation of the FPGA.