Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units

• US 6,558,967 B1
• Filed: 01/31/2001
• Issued: 05/06/2003
• Est. Priority Date: 02/17/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Multi Level Memory Technology
• Inventors: Wong, Sau-Ching
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US09/775,415
• Time in Patent Office: 825 Days
• Field of Search: 438/10, 438/11, 438/12, 438/14, 438/17, 438/18, 365/200, 365/201
• US Class Current: 438/17
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A manufacturing method for a multiple-bit-per-cell memory tests memory arrays in the memory and separately sets the number of bits stored per cell in each memory array. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. The setting of the numbers of bits per cell for the respective memory arrays can maximize the memory capacity when some arrays perform better than expected. When the memory arrays perform worse than expected, the setting of the numbers of bits per cell can salvage the memory device even if the memory cannot provide the expected memory capacity.

Claims

1. A manufacturing method comprising:

fabricating an integrated circuit memory device comprising a plurality of memory units, wherein each memory unit has a design capacity to store a maximum of Nmax bits per memory cell, wherein Nmax is greater than 1;

testing each memory unit; and

setting each memory unit for storage of Nj bits per cell, where Nj depends on results of the testing of that memory unit, wherein a total storage capacity of the integrated circuit memory device depends on the settings of the memory units.

2. The manufacturing method of claim 1, wherein:

the memory units have an expected capacity to store Nav bits per memory cell; and

when testing indicates one of the memory units can accurately write, store, and read more than Nav bits per memory cell, the setting causes that memory unit to store more than Nav bits per cell.

3. The manufacturing method of claim 1, wherein:

the memory units have an expected capacity to store Nav bits per memory cell; and

when testing indicates one of the memory units cannot accurately write, store, and read Nav bits per memory cell, the setting causes that memory unit to store fewer than Nav bits per cell.

4. The manufacturing method of claim 1, wherein:

the memory units have an expected capacity to store Nav bits per memory cell; and

the setting of the memory units causes one or more memory units to store fewer than Nav bits per memory cell, and one or more memory units to store more than Nav bits per memory cell.

5. The manufacturing method of claim 1, wherein when testing indicates one of the memory units has an unrepairable defect that prevents the memory unit from accurately storing any information in one or more memory cells, the setting sets the number Nj of bits stored per memory cell equal to zero for the memory unit containing the unrepairable defect.

6. The method of claim 1, wherein setting the memory units comprises writing the values Nj in ROM.

7. The method of claim 6, wherein writing the values Nj in ROM comprises cutting fuses in the integrated circuit memory device.

8. The method of claim 1, wherein setting the memory units comprises writing the values Nj in electrically erasable/programmable ROM.

9. The method of claim 1, wherein each memory unit comprises a memory array.