Trench schottky barrier rectifier and method of making the same

• US 6,558,984 B2
• Filed: 02/19/2002
• Issued: 05/06/2003
• Est. Priority Date: 12/15/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Amato, John E.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US10/078,994
• Publication Number:
  US 20020074578A1
• Time in Patent Office: 441 Days
• Field of Search: 438/134, 438/570, 438/576-578, 438/800
• US Class Current: 438/134
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A trench Schottky barrier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of a first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on the bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.

Claims

1. A method of forming a trench Schottky barrier rectifier, comprising:

forming a semiconductor region having first and second opposing faces, said semiconductor region comprising a drift region of first conductivity type adjacent the first face and a cathode region of said first conductivity type adjacent the second face, said drift region having a lower net doping concentration than a net doping concentration of said cathode region;

forming a plurality of trenches extending into said semiconductor region from said first face, said trenches defining a plurality of mesas within said semiconductor region and said trenches forming trench intersections at a plurality of locations;

forming an oxide layer, said oxide layer covering said semiconductor region at locations corresponding to trench bottoms and lower portions of trench sidewalls;

forming a polysilicon region, said polysilicon region being disposed within said trenches over said oxide layer;

forming insulating regions over said oxide layer at said trench intersections; and

forming an anode electrode that is adjacent to and forms a Schottky rectifying contact with said drift region.

2. The method of claim 1, further comprising providing a cathode electrode on said second face of said semiconductor region.

3. The method of claim 1, wherein said step of forming said semiconductor region comprises providing a semiconductor substrate, said semiconductor substrate corresponding to said cathode region;

and growing an epitaxial semiconductor layer on said substrate, said epitaxial layer corresponding to said drift region.

4. The method of claim 1, wherein said step of forming said trenches comprises the steps of forming a patterned masking layer over the first face of the semiconductor region and etching said trenches through said masking layer.

5. The method of claim 4, wherein said trenches are etched sufficiently deeply such that they extend through said drift region and into said cathode region.

6. The method of claim 4, wherein said trenches are etched into said drift regions, but not into said cathode region.

7. The method of claim 1, wherein the steps of forming said oxide layer, said polysilicon region, and said insulating regions further comprise:

forming an oxide layer on said first face of said semiconductor region and within said trenches;

forming a polysilicon layer over said oxide layer;

etching said polysilicon layer such that that portions of said oxide layer are exposed over said first face and portions of said oxide layer are exposed over upper portions of said trench sidewalls;

forming an insulating layer over said oxide layer and said etched polysilicon layer;

forming a patterned etch resistant layer over said insulating layer at said trench intersections; and

etching said insulating layer and said oxide layer where not covered by said patterned etch resistant layer.

8. The method of claim 7, wherein said oxide layer is thermally grown.

9. The method of claim 7, wherein said oxide layer is deposited.

10. The method of claim 7, wherein said insulating layer is a borophosphosilicate glass layer.

11. The method of claim 1, wherein said semiconductor is a silicon semiconductor.

12. The method of claim 1, wherein said first conductivity type is n-type conductivity.

13. The method of claim 1, wherein said insulating regions are borophosphosilicate glass regions.

14. A method of forming a trench Schottky barrier rectifier, comprising:

growing a silicon epitaxial layer of n-type conductivity on an n-type silicon substrate, said substrate and said epitaxial layer forming a semiconductor region having first and second opposing faces, said epitaxial layer corresponding to a drift region adjacent said first face, said semiconductor substrate corresponding to a cathode region adjacent said second face, and said drift region having a lower net doping concentration than a net doping concentration of said cathode region;

forming a plurality of trenches extending into said semiconductor region from said first face, said trenches defining a plurality of mesas within said semiconductor region, and said trenches forming trench intersections at a plurality of locations;

forming an oxide layer on said semiconductor region at said first face and within said trenches;

forming a polysilicon layer over said oxide layer;

etching said polysilicon layer such that portions of said oxide layer are exposed over said first face and over upper portions of said trench sidewalls;

forming an insulating layer over said oxide layer and said etched polysilicon layer;

forming a patterned etch resistant layer over said insulating layer at said trench intersections; and

etching said insulating layer and said oxide layer in regions where not covered by said patterned etch resistant layer; and

forming an anode electrode that is adjacent to and forms a Schottky rectifying contact with said drift region of said semiconductor region.

15. The method of claim 14, wherein said oxide layer is thermally grown.

16. The method of claim 14, wherein said oxide layer is deposited.

17. The method of claim 14, wherein said insulating regions are borophosphosilicate glass regions.