Dual silicon-on-insulator device wafer die

• US 6,558,994 B2
• Filed: 03/01/2001
• Issued: 05/06/2003
• Est. Priority Date: 03/01/2001
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Lee, Tae Jong, See, Alex, Goh, Wang Ling, Lim, Yeow Kheng, Cha, Randall Cher Liang
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Berezny, Neal
• Application Number:
  US09/841,564
• Publication Number:
  US 20020127816A1
• Time in Patent Office: 796 Days
• Field of Search: 438/155, 438/163, 438/164, 438/165, 438/967, 438/153, 438/152, 257/350, 257/351, 257/353, 257/354, 257/496, 257/348, 257/402, 257/507, 257/524, 257/352, 257/372, 257/492-3, 257/504
• US Class Current: 438/163
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76278 Vertical isolation by selective deposition of single crystal silicon, i.e. SEG techniques
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/967 Semiconductor on specified insulator

Abstract

A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Claims

1. A method for making a silicon-on-insulator semiconductor device comprising:

providing a semiconductor substrate;

depositing an insulator layer on the semiconductor substrate;

forming an opening in the insulator layer;

forming an insulator structure in a portion of the opening on the semiconductor substrate;

forming silicon on the insulator structure and the insulator layer;

forming openings in the silicon to form silicon islands;

depositing insulator in the openings;

forming gate insulators on the silicon islands; and

forming junctions in the silicon islands.

2. The method as claimed in claim 1 wherein forming the insulator structure includes:

depositing a liner oxide layer;

depositing a spacer layer;

forming a spacer on a portion of the liner oxide layer in the opening in the insulator layer; and

growing the insulator structure by thermal oxidation of the liner oxide layer not under the spacer.

3. The method as claimed in claim 2 wherein forming the insulator structure includes:

depositing a spacer layer of a nitride; and

isotropically etching the nitride to form a nitride spacer.

4. The method as claimed in claim 1 wherein forming openings in the silicon includes:

depositing an oxide layer on the silicon;

depositing a nitride layer on the oxide layer;

depositing, patterning, and developing a photoresist;

etching the nitride layer;

etching the oxide layer; and

etching the silicon.

5. The method as claimed in claim 1 wherein depositing the insulator in the openings in the silicon includes:

depositing an oxide layer on the nitride layer, on the insulator layer, on the insulator structure, and on the semiconductor substrate; and

chemical mechanical polishing the oxide layer to be coplanar with the silicon.

6. The method as claimed in claim 1 wherein forming gate insulators on the silicon islands includes depositing a gate oxide on the silicon islands and the insulator in the openings and removing the gate oxide on the insulator in the openings and on a portion of the silicon islands.

7. The method as claimed in claim 1 wherein forming the gate insulator on and the junctions in the silicon island over the insulator structure forms a partially depleted silicon-on-insulator device.

8. The method as claimed in claim 1 wherein forming the gate insulator on and the junctions in the silicon island over the insulator layer forms a fully depleted silicon-on-insulator device.

9. The method as claimed in claim 1 wherein forming the gate insulator on and the junctions in the silicon island forms a P-channel silicon-on-insulator transistor.

10. The method as claimed in claim 1 wherein forming the gate insulator on and the junctions in the silicon island forms an N-channel silicon-on-insulator transistor.

11. A method for making a silicon-on-insulator semiconductor device comprising:

providing a silicon substrate;

depositing an oxide layer on the semiconductor substrate;

forming an opening in the oxide layer;

forming an oxide structure in a portion of the opening;

forming silicon by silicon epitaxial growth on the oxide structure and the oxide layer;

forming openings in the silicon to form silicon islands;

depositing oxide in the openings;

forming gate oxides on the silicon islands; and

implanting junctions in the silicon islands.

12. The method as claimed in claim 11 wherein forming the oxide structure includes:

depositing a liner oxide layer;

depositing a nitride spacer layer;

forming a nitride spacer on a portion of the liner oxide layer in the opening in the insulator layer by isotropic etching; and

growing the oxide structure by thermal oxidation of the liner oxide layer not under the nitride spacer.

13. The method as claimed in claim 11 wherein forming openings in the silicon and filling the openings includes:

depositing an oxide layer on the silicon;

depositing a nitride layer on the oxide layer;

depositing, patterning, and developing a photoresist;

etching the nitride layer;

etching the oxide layer;

etching the silicon to form the openings;

depositing an oxide in the openings in the silicon;

depositing an oxide layer on the nitride layer, on the insulator layer, on the insulator structure, and on the semiconductor substrate; and

chemical mechanical polishing the nitride layer, the oxide layer, and the oxide to be coplanar with the silicon.