Fabrication of integrated circuits with borderless vias

• US 6,559,045 B2
• Filed: 06/12/2002
• Issued: 05/06/2003
• Est. Priority Date: 06/09/1999
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Alliedsignal Inc. (Honeywell International Inc.)
• Inventors: Chung, Henry
• Primary Examiner(s): Ngô , Ngân V.
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US10/170,612
• Publication Number:
  US 20020158283A1
• Time in Patent Office: 328 Days
• Field of Search: 438/622-624, 438/631, 438/633, 438/518, 438/597, 257/758-760
• US Class Current: 438/622
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/02351 treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/3124 layers comprising hydrogen silsesquioxane
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.

Claims

1. A process for producing an integrated circuit structure which comprises

(a) providing a substrate;

(b) depositing a layer of a second dielectric material on the substrate;

(c) forming a pattern of metal contacts on the layer of the second dielectric material;

(d) conformally depositing a lining of a first dielectric material on side walls of the metal contacts, on a top surface of the metal contacts, and on a floor of a space between the metal contacts on the layer of the second dielectric material;

(e) removing the first dielectric material from the top surface of the metal contacts while retaining the first dielectric material lining on the side walls of the metal contacts;

(f) depositing an additional layer of the second dielectric material on the top surface of the metal contacts and in the space between adjacent linings of the metal contacts;

(g) depositing a layer of a sacrificial metal on the additional layer of the second dielectric material;

(h) depositing a layer of a photoresist on the layer of the sacrificial metal layer;

(i) imagewise removing a portion of the photoresist over at least one metal contact and optionally over at least a portion of the lining of first dielectric material on a side wall of a metal contact;

(j) removing the portion of the layer of the sacrificial metal under the removed portion of the photoresist;

(k) removing the balance of the photoresist layer, and removing the portion of the additional layer of the second dielectric material under the removed portion of the sacrificial metal layer until at least one metal contact and optionally a lining on a side wall of a metal contact is reached thus forming at least one via through the second dielectric material extending to at least one metal contact and optionally a lining of a side wall of a metal contact.

2. The process of claim 1 further comprising:

(l) depositing a layer of a barrier metal on the sacrificial metal layer, and on inside walls and a floor of the at least one via;

(m) filling the at least one via with a fill metal and depositing a layer of a fill metal on the layer of the barrier metal;

(n) removing the fill metal layer, the barrier metal layer and the sacrificial metal layer.

3. The process of claim 1 wherein step (e) further comprises removing the first dielectric material from the floor of the space between the metal contacts.

4. The process of claim 2 wherein step (e) further comprises removing the first dielectric material from the floor of the space between the metal contacts.

5. The process of claim 1 wherein the first dielectric material is organic and the second dielectric material is inorganic.

6. The process of claim 1 wherein the first dielectric material is inorganic and the second dielectric material is organic.

7. The process of claim 2 wherein the first dielectric material is organic and the second dielectric material is inorganic.

8. The process of claim 2 wherein the first dielectric material is inorganic and the second dielectric material is organic.

9. The process of claim 3 wherein the first dielectric material is organic and the second dielectric material is inorganic.

10. The process of claim 3 wherein the first dielectric material is inorganic and the second dielectric material is organic.

11. The process of claim 4 wherein the first dielectric material is organic and the second dielectric material is inorganic.

12. The process of claim 4 wherein the first dielectric material is inorganic and the second dielectric material is organic.

13. A process for producing an integrated circuit structure which comprises

(a) providing a substrate;

(b) depositing a layer of a third dielectric material on the substrate;

(c) forming a pattern of metal contacts on the layer of the third dielectric material;

(d) conformally depositing a lining of a first dielectric material on side walls of the metal contacts, on a top surface of the metal contacts, and on a floor of a space between the metal contacts on the layer of the third dielectric material;

(e) removing the first dielectric material from the top surface of the metal contacts while retaining the first dielectric material lining on the side walls of the metal contacts;

(f) depositing a layer of a second dielectric material on the top surface of the metal contacts and in the space between adjacent linings of the metal contacts;

(g) depositing an additional layer of the third dielectric material on the layer of the second dielectric material;

(h) depositing a layer of a photoresist on the additional layer of the third dielectric material;

(i) imagewise removing a portion of the photoresist over at least one metal contact and optionally over at least a portion of the lining of first dielectric material on a side wall of a metal contact;

(j) removing the portion of the additional layer of the third dielectric material under the removed portion of the photoresist;

(k) removing the balance of the photoresist layer, and removing the portion of the second dielectric material under the removed portion of the additional layer of the third dielectric material until at least one metal contact and optionally a lining on a side wall of a metal contact is reached thus forming at least one via through the second dielectric material extending to at least one metal contact and optionally a lining of a side wall of a metal contact.

14. The process of claim 13 further comprising:

(l) depositing a layer of a barrier metal on the additional layer of the third dielectric, and on the inside walls and a floor of the at least one via;

(m) filling the at least one via with a fill metal and depositing a layer of a fill metal on the layer of the barrier metal;

(n) removing the fill metal layer, the barrier metal layer and the sacrificial metal layer.

15. The process of claim 13 wherein step (e) further comprises removing the first dielectric material from the floor of the space between the metal contacts.

16. The process of claim 14 wherein step (e) further comprises removing the first dielectric material from the floor of the space between the metal contacts.

17. The process of claim 13 wherein the first and third dielectric materials are organic and the second dielectric material is inorganic.

18. The process of claim 13 wherein the first and third dielectric materials are inorganic and the second dielectric material is organic.

19. The process of claim 14 wherein the first and third dielectric materials are organic and the second dielectric material is inorganic.

20. The process of claim 14 wherein the first and third dielectric materials are inorganic and the second dielectric material is organic.

21. The process of claim 15 wherein the first and third dielectric materials are organic and the second dielectric material is inorganic.

22. The process of claim 15 wherein the first and third dielectric materials are inorganic and the second dielectric material is organic.

23. The process of claim 16 wherein the first and third dielectric materials are organic and the second dielectric material is inorganic.

24. The process of claim 16 wherein the first and third dielectric materials are inorganic and the second dielectric material is organic.