P-n heterojunction-based structures utilizing HVPE grown III-V compound layers

• US 6,559,467 B2
• Filed: 05/17/2001
• Issued: 05/06/2003
• Est. Priority Date: 11/18/1997
• Status: Expired due to Term

• Current Assignee: Kyma Technologies, Inc.
• Original Assignee: Technologies And Devices International Inc.
• Inventors: Melnik, Yuri V., Dmitriev, Vladimir A., Vassilevski, Konstantin V., Nikolaev, Audrey E.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US09/860,834
• Publication Number:
  US 20020053679A1
• Time in Patent Office: 719 Days
• Field of Search: 257/94-103, 257/90, 257/76, 257/183-186, 257/191, 257/12-17, 257/14-15, 257/22, 257/25, 257/33
• US Class Current: 257/12
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0259 Microstructure
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 31/0304 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials

Abstract

A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of Al_xB_yIn_zGa_1-x-y-zN, InGaN_1-a-bP_aAs_b, or Al_xB_yIn_zGa_1-x-y-zN_1-a-bP_aAs_b.

Claims

1. A III-V p-n heterojunction device, comprising:

a substrate;

a first high temperature n-type III-V compound layer grown directly on said substrate, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 900°

C. using HVPE techniques, wherein a low temperature buffer layer is not interposed between said substrate and said high temperature n-type III-V compound layer;

a second n-type III-V compound layer grown using HVPE techniques, wherein said second n-type III-V compound layer is grown directly on said first high temperature n-type III-V compound layer, wherein said second n-type III-V compound layer is an active layer of said III-V p-n heterojunction device; and

a p-type III-V compound layer grown directly on said second n-type III-V compound layer using HVPE techniques, said p-type III-V compound layer forming a p-n heterojunction with said second n-type III-V compound layer.

2. The III-V p-n heterojunction device of claim 1, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 950°

C. using HVPE techniques.

3. The III-V p-n heterojunction device of claim 1, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 1000°

C. using HVPE techniques.

4. The III-V p-n heterojunction device of claim 1, further comprising:

a first contact deposited on said p-type III-V compound layer; and

a second contact deposited on said substrate.

5. The III-V p-n heterojunction device of claim 4, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

6. The III-V p-n heterojunction device of claim 1, further comprising a second p-type III-V compound layer grown on said p-type III-V compound layer using HVPE techniques.

7. The III-V p-n heterojunction device of claim 6, further comprising:

a first contact deposited on said second p-type III-V compound layer; and

a second contact deposited on said substrate.

8. The III-V p-n heterojunction device of claim 7, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

9. The III-V p-n heterojunction device of claim 1, wherein said first high temperature n-type III-V compound layer is comprised of AlGaN, said second n-type III-V compound layer is comprised of GaN, and said p-type III-V compound layer is comprised of AlGaN.

10. The III-V p-n heterojunction device of claim 6, wherein said first high temperature n-type III-V compound layer is comprised of AlGaN, said second n-type III-V compound layer is comprised of GaN, said p-type III-V compound layer is comprised of AlGaN, and said second p-type III-V compound layer is comprised of GaN.

11. The III-V p-n heterojunction device of claim 1, wherein said substrate is selected from the group of materials consisting of sapphire, silicon carbide, gallium nitride, and silicon.

12. The III-V p-n heterojunction device of claim 1, wherein said p-type III-V compound layer includes at least one acceptor impurity metal selected from the group of metals consisting of Mg, Zn, and MgZn.

13. The III-V p-n heterojunction device of claim 12, wherein a concentration of said at least one acceptor impurity metal within said p-type III-V compound layer is in the range of 10¹⁸ to 10²¹ atoms cm⁻

3.

14. The III-V p-n heterojunction device of claim 12, wherein a concentration of said at least one acceptor impurity metal within said p-type III-V compound layer is in the range of 10¹⁹ to 10²⁰ atoms cm⁻

3.

15. The III-V p-n heterojunction device of claim 12, wherein said p-type III-V compound layer is co-doped with O.

16. The III-V p-n heterojunction device of claim 6, wherein said second p-type III-V compound layer includes at least one acceptor impurity metal selected from the group of metals consisting of Mg, Zn, and MgZn.

17. The III-V p-n heterojunction device of claim 16, wherein a concentration of said at least one acceptor impurity metal within said second p-type III-V compound layer is in the range of 10¹⁸ to 10²¹ atoms cm⁻

3.

18. The III-V p-n heterojunction device of claim 16, wherein a concentration of said at least one acceptor impurity metal within said second p-type III-V compound layer is in the range of 10¹⁹ to 10²⁰ atoms cm⁻

3.

19. The III-V p-n heterojunction device of claim 16, wherein said second p-type III-V compound layer is co-doped with O.

20. The III-V p-n heterojunction device of claim 1, wherein said second n-type III-V compound layer includes at least one donor impurity selected from the group of materials consisting of O, Si, Ge, and Sn.

21. The III-V p-n heterojunction device of claim 1, wherein a first band gap corresponding to said second n-type III-V compound layer is narrower than a second band gap corresponding to said first high temperature n-type III-V compound layer, and wherein said first band gap is narrower than a third band gap corresponding to said p-type III-V compound layer.

22. A III-V p-n heterojunction device, comprising:

a substrate;

a high temperature n-type AlGaN layer is grown directly on said substrate, wherein said high temperature n-type AlGaN layer is grown at a temperature greater than 900°

C. using HVPE techniques, wherein a low temperature buffer layer is not interposed between said substrate and said high temperature n-type AlGaN layer;

an n-type GaN layer grown directly on said high temperature n-type AlGaN layer using HVPE techniques, wherein said n-type GaN layer is an active layer of said III-V p-n heterojunction device;

a p-type AlGaN layer grown directly on said n-type GaN layer using HVPE techniques, said p-type AlGaN layer forming a p-n heterojunction with said n-type GaN layer; and

a p-type GaN layer grown directly on said p-type AlGaN layer using HVPE techniques.

23. The III-V p-n heterojunction device of claim 22, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 950°

C. using HVPE techniques.

24. The III-V p-n heterojunction device of claim 22, wherein said high temperature n-type III-V compound layer is grown at a temperature greater than 1000°

C. using HVPE techniques.

25. The III-V p-n heterojunction device of claim 22, further comprising:

a first contact deposited on said p-type GaN layer; and

a second contact deposited on said substrate.

26. The III-V p-n heterojunction device of claim 25, wherein said first and second contacts are selected from the group of materials consisting of nickel, palladium, gold, platinum, gold-nickel, and palladium-platinum.

27. The III-V p-n heterojunction device of claim 22, wherein said substrate is selected from the group of materials consisting of sapphire, silicon carbide, gallium nitride, and silicon.

28. The III-V p-n heterojunction device of claim 22, wherein said p-type AlGaN layer and said p-type GaN layer each include at least one acceptor impurity metal selected from the group of metals consisting of Mg, Zn, and MgZn.

29. The III-V p-n heterojunction device of claim 28, wherein a concentration of said at least one acceptor impurity metal within said p-type AlGaN layer is in the range of 10¹⁸ to 10²¹ atoms cm⁻

3, and wherein a concentration of said at least one acceptor impurity metal within said p-type GaN layer is in the range of 10¹⁸ to 10²¹ atoms cm<sup>−

3</sup>.

30. The III-V p-n heterojunction device of claim 28, wherein a concentration of said at least one acceptor impurity metal within said p-type AlGaN layer is in the range of 10¹⁹ to 10²⁰ atoms cm⁻

3, and wherein a concentration of said at least one acceptor impurity metal within said p-type GaN layer is in the range of 10¹⁹ to 10²⁰ atoms cm<sup>−

2</sup>.

31. The III-V p-n heterojunction device of claim 28, wherein said p-type AlGaN layer is co-doped with O.

32. The III-V p-n heterojunction device of claim 28, wherein said p-type GaN layer is co-doped with O.

33. The III-V p-n heterojunction device of claim 22, wherein said n-type GaN layer includes at least one donor impurity selected from the group of materials consisting of O, Si, Ge, and Sn.