Test pattern for evaluating a process of silicide film formation

• US 6,559,475 B1
• Filed: 11/03/2000
• Issued: 05/06/2003
• Est. Priority Date: 05/25/2000
• Status: Expired due to Fees

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Jong-Chae
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US09/704,760
• Time in Patent Office: 914 Days
• Field of Search: 257/48, 324/765, 324/766, 324/671, 324/716, 355/133, 438/18
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention relates to a semiconductor device, and more particularly, to a test pattern for evaluating a process of silicide film formation. The test pattern in accordance with the present invention includes: a silicon substrate having an active region and a field region; a first pattern composed of a cross resistor pattern of a polycide layer formed on the field region; and a second pattern composed of polycide layer and a silicide layer formed on the active region. The second pattern includes: a pair of polycide patterns composed of a first polycide strip and a second polycide strip extended in parallel, being spaced from each other a predetermined interval on an insulating film formed on the active region; and an active silicide strip formed between the first polycide strip and the second polycide strip.

Claims

1. A test pattern, comprising:

a first polycide strip and a second polycide strip extending along a first direction separated by a prescribed distance on an insulating film;

first contact pads coupled to both lateral ends of each of the first and second polycide strips;

a silicide strip between respective interior lateral sides of the first polycide strip and the second polycide strip; and

second contact pads coupled to lateral ends of the silicide strip, wherein the first and second contact pads each comprise current contact pads and voltage contact pads, respectively.

2. The test pattern of claim 1, wherein the first and second polycide strips are separate and independent from one another.

3. The test pattern of claim 1, wherein the polycide and silicide strips comprise a first pattern formed over an active region of a semiconductor substrate, wherein the test pattern further comprises a second pattern formed over a field region that determines a sheet resistance of the polycide strips.

4. The test pattern of claim 3, wherein the test pattern is a pattern capable of determining one of a manufactured width of the silicide strip and a manufactured resistance of the silicide strip by electrically measuring current and voltage using the first and second contact pads.

5. The test pattern of claim 1, wherein the test pattern is a pattern that determines one of a manufactured width of the silicide strip and a manufactured resistance of the silicide strip by automatically measuring current and voltage using the first and second contact pads.

6. The test pattern of claim 1, further comprising two third contact pads located between the first contact pads coupled to both lateral ends of the first or second polycide strip.

7. The test pattern of claim 6, wherein the third contact pads comprise voltage contact pads.

8. The test pattern of claim 1, further comprising two third contact pads coupled to either the first or the second polycide strip.

9. A test pattern, comprising:

a silicon substrate having an active region and a field region;

a first pattern that determines a sheet resistance of a polycide layer on the field region; and

a second pattern including polycide layer patterns and a silicide layer formed over the active region, wherein the second pattern comprises,

a pair of polycide layer patterns composed of a first polycide strip and a second polycide strip extended in parallel, being spaced from each other a predetermined interval on an insulating film formed on the active region,

first and second current contact pads each coupled to lateral ends of the first polycide strip,

first and second voltage contact pads coupled to the first polycide strip between the first and second current contact pads,

third and fourth current contact pads each coupled to lateral ends of the second polycide strip,

third and fourth voltage contact pads coupled to the second polycide strip between the third current contact pad and the fourth current contact pad, and

an active silicide strip having prescribed dimensions between the first polycide strip and the second polycide strip.

10. The test pattern of claim 9, further comprising:

fifth and sixth current contact pads respectively coupled to first and second ends of the active silicide strip; and

fifth and sixth voltage contact pads respectively coupled to the second and first ends of the active silicide strip.

11. The test pattern of claim 10, wherein the second pattern determines a line width of the active silicide strip by measuring line widths of the first polycide strip and the second polycide strip using the current and voltage contact pads.

12. The test pattern of claim 11, wherein the first pattern is a cross resistor pattern.

13. A test pattern, comprising:

a silicon substrate having an active region and a field region;

a first pattern composed of a cross resistor pattern of a polycide layer formed on the field region; and

a second pattern composed of polycide layer patterns and a silicide layer formed on an insulation layer over the active region,

wherein the first pattern comprises;

two polycide layer patterns having the same width formed to be orthogonal to each other;

a first current contact pad and a first voltage contact pad each connectively formed at the lateral ends of one of the polycide layer patterns; and

a second current contact pad and a second voltage contact pad each connectively formed at the lateral ends of the other polycide layer pattern, and wherein,

the second pattern comprises;

a pair of polycide layer patterns composed of a first polycide strip and a second polycide strip extended in parallel, being spaced from each other a predetermined interval on an insulating film formed on the active region;

third and fourth current contact pads each connected to the lateral ends of the first polycide strip;

third and fourth voltage contact pads connectively formed on the first polycide strip between the third and fourth current contact pads;

fifth and sixth current contact pads each connectively formed at the lateral ends of the second polycide strip;

fifth and sixth voltage contact pads connectively formed on the second polycide strip between the fifth current contact pad and the sixth current contact pad;

an active silicide strip formed over the active region between the first polycide strip and the second polycide strip;

seventh and eighth current contact pads each connectively formed at the ends of the active silicide strip; and

seventh and eighth voltage contact pads each connectively formed at the ends of the active silicide strip.

14. The test pattern of claim 13, wherein the first pattern is a test pattern for evaluating the sheet resistance of the polycide layer on the field region.

15. The test pattern of claim 13, wherein the second pattern is a pattern for indirectly evaluating a line width of the active silicide strip by measuring the line widths of the first polycide strip and second polycide strip of the second pattern by an electrical method.

16. The test pattern of claim 13, wherein the first current contact pad and the fifth current contact pad share the same pad, and the second current contact pad and the sixth current contact pad share the same pad.